United States

5G, Beyond 5G and 6G phased arrays for communications and sensing are being developed for consumer use. The communication system requirements lead to a few phased array architectures, package and semiconductor process options which then impact common reliability concerns and challenges. Integrated system and technology co-design offers opportunities for improvements in the handset and adjacent device spaces.

IRPS 2024 Main Conference

Reliability Considerations for 5G and 6G Phased Arrays

communications systems

phased array

power amplifier

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

Please register for educational events at the following link: https://www.registerme.eu/event/esscirc-essderc-2021/

Please register for the ESSCIRC/ESSDERC Educational Events to join the event.

ESSCIRC ESSDERC Educational Events

The Educational Events of ESSCIRC ESSDERC 2021. 

technical paper

#### Welcome to the 62nd IEEE International Reliability Physics Symposium (IRPS)! 
**The 2024 IEEE International Reliability Physics Symposium (IRPS) was held in Dallas, Texas from April 14 to 18, 2024.** 

[![](https://assets.underline.io/uploads/markdown_image/1/image/9cc005f94b4ba4a81918eb49e0a51057.png)](https://underline.io/events/446/reception)
[![](https://assets.underline.io/uploads/markdown_image/1/image/acae953ba70ae2a57eed7b0250d6dd7d.png)](https://www.irps.org/)
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**[IRPS 2024 eGuide](https://drive.google.com/file/d/1DHxkWbafodK_D2HlDi7lwRK7KatgBgBD/view?usp=drive_link)** 
Please save the zip file locally and click the "start.pdf" to view the file. 
 
**IRPS 2024 General Chair Welcome Message**

On behalf of the Management Committee of the IEEE International Reliability Physics Symposium (IRPS) and the IRPS Board of Directors, it gives me great pleasure to extend a warm welcome to all who are planning to attend the IRPS 2024, scheduled to take place from April 14-18, 2024, in Dallas, TX. 
Over its 62-year history, IRPS has solidified its position as the premiere conference for engineers and scientists to present new and original work in the field of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and other parts of the world, IRPS aims to deepen our understanding of reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS offers diverse opportunities for attendees to enhance their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The IRPS 2024 technical activities will begin with two days of a total of twenty tutorial sessions covering a broad spectrum of emerging reliability topics beyond CMOS device, circuit and system reliability. These sessions are devoted to both newcomers as well as experts. Three reliability Year in Review (YIR) talks focusing on neuromorphic computing, dielectric breakdown in leading edge devices, and GaN technology will be provided on Monday after the tutorials.

The IRPS 2024 technical program will feature four distinguished keynote talks in the plenary sessions delivered by Prof. Shinichi Takagi from The University of Tokyo and Dr. Su Jin Ahn from Samsung on Tuesday, Dr. Rajeev Malik from IBM on Wednesday, and Dr. Sameer Pendharkar from Texas Instruments on Thursday. The technical program, organized into three parallel tracks, consists of contributed and seventeen invited papers from leaders in industry and academia. Additionally, two invited talks by recipients of paper awards from our sister conferences, European Symposium on Reliability of Electron Device Failure Physics and Analysis (ESREF) 2023 and the International Integrated Reliability Workshop (IIRW) 2023, will be given in the technical program. 

Tuesday evening will host ten workshops, offering an opportunity for in-depth, face-to-face discussions on emerging reliability challenges, including the three IRPS 2024 focus topics. A poster session will be held in the Austin Ranch outside the symposium building on Wednesday evening. Both events are sure to be lively. The IRPS 2024 and the International ESD Workshop (IEW) will be co-hosted with IEW registrants participating in both IRPS and IEW programs.

The IRPS 2024 will adopt a hybrid conference style, allowing virtual access to live oral presentations hosted by the Underline. Real-time streaming of all technical events (excluding Workshops and Posters) will be available in the US Central Timezone, providing virtual attendees with Q&A opportunities. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees after the symposium. All authors will be presenting in person.

Finally, I would like to extend my extreme gratitude to our patrons, exhibitors, and all participants for their invaluable support, which makes IRPS successful. 

Please enjoy the IRPS 2024!

Koji Eriguchi, General Chair 
of 2024 IRPS Management Committee
 
**About IRPS** 
The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. 

In this paper, we examine the impact of recently introduced low thermal budget HKMG treatments on stress-induced leakage current and defect generation in pMOS devices. We also conduct time-dependent dielectric breakdown measurements to analyze Soft-Breakdown behavior and compare extrapolated lifetimes with conventional high-performance logic devices. Additionally, we explore the effects of a new low-temperature treatment that enhances the quality of the high-k (HK) layer to meet high-temperature  TDDB standards.

SILC and TDDB reliability of novel low thermal budget RMG gate stacks

We study oxygen flow role during IGZO PVD process on high temperature PBTI in back-gated TFTs by combining light-assisted with electrical stress measurements. Oxygen flow is observed to affect the magnitude of charge trapping and hydrogen related channel doping during PBTI. We show a correlation between sub-gap DOS and oxygen flow during deposition: the larger the oxygen flow, the smaller the light response at time-zero and its increase during PBTI, despite a larger negative DVth. 

Light-assisted investigation of the role of oxygen flow during IGZO deposition on deep subgap states and their evolution under PBTI

A full characterization of deep-level-effects in N-polar GaN-based-HEMTs has been carried out by means of Drain-Current-Transient-Spectroscopy (DCTS). The effect of ohmic-contacts, composition of AlGaN-cap-layer, and of the quality of the epitaxial layers have been studied. We show that the occurrence of the “antidispersion”  (ID transient increase during pulsed-measurements), due to negative-shift of threshold-voltage, is related to Fe-related-defects ionization. Through device and epitaxy optimization, dispersion-free devices, showing a 15% transient increase of drain current were obtained.

Deep level effects in N-polar AlGaN/GaN High Electron Mobility Transistors: towards zero dispersion effects

Thermal behavior and its effect on RF large signal aging is extensively studied using Power Amplifier. While strong Iddq increase in linear region is seen, no significant change in RF is observed in compression. RF stress at three different VDD and Tj is reported. Thermal imaging results validate  TA Vs Tj  at Pdiss. Time domain peak voltage swings at different Tj demonstrate that HCIand off-state TDDB are key degradation mechanisms demonstrating excellent thermal behavior.

Thermal considerations on RF reliability and aging in SOI CMOS based Power Amplifiers

The lithium-ion battery experiences catastrophic failure as its health degrades rapidly (knee-point failure). The majority of prior models focus on estimating battery health during its usage phase. This study proposes a cell lifetime degradation model that addresses all three phases of battery life: calendar aging, cycle aging, and post-knee aging.  Experimental data has been used to build individual models for the three stages which have later been combined to form the cell lifetime degradation model. 

Cell Lifetime Degradation Model Development for Li-Ion Coin Cells considering Calendar Aging and Post-Knee Degradation

This paper proposes a virtual FA (vFA), a new methodology that helps identify failures in field using the telemetry data. The telemetry data refers to the information that is generated when DRAM product is deployed in customer’s data center and information is generated and collected when faults occur in the field. Through this, risk can be accurately predicted and improvement activities can be carried out quickly.

Virtual FA methodology for DRAM: Real-time analysis and prediction method using Telemetry, Field data

This paper presents transformer-based deep learning approach for outlier detection, reducing DPPM while maintaining competitive testing costs. Outlier ICs are identified by comparing deep learning-predicted parameters and corresponding measured values. Comparative analysis with D-PAT, NNR, and machine learning approaches validates our method's superior DPPM reduction: 62% compared to D-PAT, 13% compared to NNR, and 8% compared to machine learning method. Physical analysis confirms our method's sensitivity to latent defects, highlighting cost-effectiveness in achieving automotive-grade quality.

Utilizing Transformer Deep Learning Based Outlier Detection to Screen Out Reliability Weak ICs

Compared to FinFET, MBCFET has significant structural differences such as nanosheet channel with variable width and dielectric spacer between inner gate and highly doped diffusion region. Nanosheet width and spacer architecture play a crucial role in device performance and enable the design of devices with different advantages and disadvantages. We overview the impact of MBCFET 's unique structures on device characteristics and also analyze the reliability impact of MBCFET's unique structures. 

Device Design and Reliability of GAA MBCFET

PBTI for scaled E-Mode High-K GaN-Transistors with ultra-thin Tox &lt; 21.5Å on 300mm diameter GaN-on-Si wafer is studied for the first time. PBTI-degradation rate is shown to decrease over time to reach saturation. Study indicates prevalence of near-interface-traps generated during stress. A phenomenological model is introduced to describe the saturating BTI-degradation dynamics. Despite PBTI-degradation with DVT saturating at ~350mV, the GaN-MOSHEMT Figure-of-Merit gain is projected to be &gt;~15X better than industry-standard Si LDMOS and pGaN-HEMT/GaN-JFET.

PBTI in Scaled Oxide Submicron Enhancement Mode High-K Gallium Nitride Transistors

We show FeFET-based reservoir computing with notable robustness against charge trapping-induced interface degradation in silicon FeFETs, which is known to be critical when operating as nonvolatile memory devices. This reliability concern is mitigated when employed for reservoir computing, which leverages the dynamic property instead of the static property of FeFETs. A degradation-robust FeFET reservoir can be trained to classify spoken-digit dataset, where gt;10k of write operations were applied during data processing, with high classification accuracy.

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SILC and TDDB reliability of novel low thermal budget RMG gate stacks

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