United States

This study focuses on utilizing high voltage capacitance-voltage (HV-CV) analysis to investigate the correlation between defect generation regions and field plates (FPs) in pGaN HEMT devices. We combine ID-VG with C-V to show that optimized process not only enhances performance, but also improves reliability, particularly below the FP near the gate.

IRPS 2024 Main Conference

HV-CV Analysis Trapping Behavior in 650V pGaN HEMT with Field Plates for High-Voltage Power Applications

field plate

reliability

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

ESSCIRC ESSDERC 2021

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





technical paper

#### Welcome to the 62nd IEEE International Reliability Physics Symposium (IRPS)! 
**The 2024 IEEE International Reliability Physics Symposium (IRPS) was held in Dallas, Texas from April 14 to 18, 2024.** 

[![](https://assets.underline.io/uploads/markdown_image/1/image/9cc005f94b4ba4a81918eb49e0a51057.png)](https://underline.io/events/446/reception)
[![](https://assets.underline.io/uploads/markdown_image/1/image/acae953ba70ae2a57eed7b0250d6dd7d.png)](https://www.irps.org/)
[![](https://assets.underline.io/uploads/markdown_image/1/image/e1806748f2fc69f825e596872a7afdfd.png)](https://drive.google.com/drive/folders/1SmhpLZD9swYxrfP0TYF6327QTIciy3tV?usp=drive_link)
 

**[IRPS 2024 eGuide](https://drive.google.com/file/d/1DHxkWbafodK_D2HlDi7lwRK7KatgBgBD/view?usp=drive_link)** 
Please save the zip file locally and click the "start.pdf" to view the file. 
 
**IRPS 2024 General Chair Welcome Message**

On behalf of the Management Committee of the IEEE International Reliability Physics Symposium (IRPS) and the IRPS Board of Directors, it gives me great pleasure to extend a warm welcome to all who are planning to attend the IRPS 2024, scheduled to take place from April 14-18, 2024, in Dallas, TX. 
Over its 62-year history, IRPS has solidified its position as the premiere conference for engineers and scientists to present new and original work in the field of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and other parts of the world, IRPS aims to deepen our understanding of reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS offers diverse opportunities for attendees to enhance their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The IRPS 2024 technical activities will begin with two days of a total of twenty tutorial sessions covering a broad spectrum of emerging reliability topics beyond CMOS device, circuit and system reliability. These sessions are devoted to both newcomers as well as experts. Three reliability Year in Review (YIR) talks focusing on neuromorphic computing, dielectric breakdown in leading edge devices, and GaN technology will be provided on Monday after the tutorials.

The IRPS 2024 technical program will feature four distinguished keynote talks in the plenary sessions delivered by Prof. Shinichi Takagi from The University of Tokyo and Dr. Su Jin Ahn from Samsung on Tuesday, Dr. Rajeev Malik from IBM on Wednesday, and Dr. Sameer Pendharkar from Texas Instruments on Thursday. The technical program, organized into three parallel tracks, consists of contributed and seventeen invited papers from leaders in industry and academia. Additionally, two invited talks by recipients of paper awards from our sister conferences, European Symposium on Reliability of Electron Device Failure Physics and Analysis (ESREF) 2023 and the International Integrated Reliability Workshop (IIRW) 2023, will be given in the technical program. 

Tuesday evening will host ten workshops, offering an opportunity for in-depth, face-to-face discussions on emerging reliability challenges, including the three IRPS 2024 focus topics. A poster session will be held in the Austin Ranch outside the symposium building on Wednesday evening. Both events are sure to be lively. The IRPS 2024 and the International ESD Workshop (IEW) will be co-hosted with IEW registrants participating in both IRPS and IEW programs.

The IRPS 2024 will adopt a hybrid conference style, allowing virtual access to live oral presentations hosted by the Underline. Real-time streaming of all technical events (excluding Workshops and Posters) will be available in the US Central Timezone, providing virtual attendees with Q&A opportunities. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees after the symposium. All authors will be presenting in person.

Finally, I would like to extend my extreme gratitude to our patrons, exhibitors, and all participants for their invaluable support, which makes IRPS successful. 

Please enjoy the IRPS 2024!

Koji Eriguchi, General Chair 
of 2024 IRPS Management Committee
 
**About IRPS** 
The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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To access the site please register [**here**](https://www.irps.org/registration-fees). 

Please register!

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. 

This work provides a characterization and modeling of the mechanisms responsible for the vertical loss (VL) of charge in charge trap 3D NAND arrays. Contributions of charge detrapping and storage charge loss (SCL) are experimentally separated for the first time. Studying the dependence of SCL activation energy on cycling and programmed level, evidence for the physical mechanisms contributing to it is provided. Finally, a simple yet effective model is devised which reproduces the VL transients.

Experimental Segmentation of Vertical Charge Loss Mechanisms in Charge Trap-Based 3D NAND Arrays

The impact of Program/Erase (P/E) cycling on Cell VT Distribution (CVD) during retention bake in 3-D NAND Charge Trap Flash (CTF) arrays is modeled. Experimental data under Solid Pattern (SP) test is analyzed using Activated Barrier Double Well Thermionic (ABDWT) model. Only two adjustable parameters can model DR loss across various P/E cycles, Bake Temperature (BT), Programming Levels (PL) and CVD levels (sigma). The relative contributions from the underlying physical mechanisms are determined.

Modeling of Post-Cycling Retention Bake in 3-D CTF TLC NAND Arrays

SiC MOSFETs are key components for car electrification, the killer application being the traction inverter with power levels of 100+kW. This requires modules containing tens of SiC die, which, combined with the harsh temperature requirements, puts severe constraints on the reliability of the individual SiC die. This paper will discuss both the extrinsic and intrinsic reliability challenges of SiC MOSFETs, and the approaches and modeling of gate related failure modes (HTGB, ALT-HTRB and cosmic rays).

On the Intrinsic and Extrinsic Reliability Challenges of SiC MOSFETs

We have performed high resolution conductance measurements in a wide range of frequency from 1 Hz-10 MHz on thermally oxidized and NO annealed MOS capacitors. We identified the energetic position of fast and slow border traps with respect to EC of SiC and estimated the σc and their location in the oxide. In the final paper, we will provide a comparative analysis of border traps across a range of samples, with distinct annealing treatments.

Exploring the border traps near the SiO2-SiC interface using low frequency conductance measurements

Accurate prediction of EM-induced MTTF for on-chip power/ground grids with advanced EDA tools requires knowledge of geometry dependent random  parameters such as copper grain size, atomic diffusivity, resistivity, critical stress, and their distributions. A unified model describing resistance evolution in the segments with arbitrary geometries and loads can address this challenge. This paper presents such a model and demonstrates its predictive power by comparison with experimental data from the 12 nm GlobalFoundries FinFET technology node.

A Unified Physics-Based Stochastic Model for EM-Induced Resistance Degradation in BEoL Interconnect Segments

Product reliability, encompassing both manufacturing and operational aspects, is emerging as a crucial aspect of design across iterative chip-package-system design cycles, especially those products anticipated to endure for longer lifetime and possible severe operation environment, necessitate careful consideration of Multiphysics-based reliability enhancements while addressing the interdependencies among different reliability requirements. This paper introduces the innovative EDA solution on Design for Reliability (DFR) workflow with Multiphysics consideration, crossing from IP level, chip, and package/PCB levels. 

Design for Reliability (DFR) Aware EDA Solution for Product Reliability

This paper reviews the reliability of Solid-State Drives (SSDs) based on NAND Flash memory with a focus comparing enterprise SSDs using TLC and QLC NAND. The paper analyzes various datasets including internal qualification methods and field studies. The data indicates that QLC SSDs have similar reliability to TLC SSDs, when NAND reliability mechanisms are sufficiently mitigated. Tradeoffs related to NAND differences and reliability mitigations and the resulting effect on performance, QoS, and endurance are highlighted.

Comparing the Reliability of Solid-State Drives Based on TLC and QLC NAND Flash Memories

Bipolar switching between accumulation and inversion can result in an unexpected threshold voltage drift in SiC MOSFETs. This gate switching instability (GSI) is significantly larger than what is known for bias temperature instability (BTI). Based on the similarity to charge pumping experiments, we develop a comprehensive physical model for GSI based on recombination enhanced defect reactions, derive a closed form analytical solution, and finally validate the model against detailed experimental data.

A Recombination-Enhanced-Defect-Reaction-Based Model for the Gate Switching Instability in SiC MOSFETs

Predicting aging behavior is essential for product development to ensure in-field lifetime. Conventionally, aging margin is determined by identifying the maximum value of Vmin shifts through a series of HTOL tests. In this paper, we propose a machine learning-based methodology to predict Vmin shifts. Compared to the conventional aging margin, this methodology offers & 20% reduction of aging margin. Besides, it demonstrates 3x sensitivity to NBTI than on-chip NOR for applications in automotive products.

Vmin Shift Prediction Using Machine Learning-Based Methodology for Automotive Products

NBTI of IGZO TFTs is studied using diverse devices and conditions. Four main characteristics are observed: V th shift is almost independent of V g_stress, and shows a large activation energy and a steep time kinetic, while the relaxation rate decreases with increasing temperatures. Using TCAD and modelling, these peculiar features can be explained by an oxide-field-dominated hydrogen release at gate side of the gate-dielectric, inducing additional doping and the negative V th shift.

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Experimental Segmentation of Vertical Charge Loss Mechanisms in Charge Trap-Based 3D NAND Arrays

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