United States

In recent years, oxide electronics has emerged as one of the most promising new technologies for a variety of electrical and optoelectronic applications, including next-generation displays, solar cells, batteries, and photodetectors. Oxide electronics have a lot of potential because of their high carrier mobilities and ability to be manufactured at low temperatures. However, the preponderance of oxide semiconductors is n-type oxides, limiting present applications to unipolar devices and stifling the development of oxide-based bipolar devices like p-n diodes and complementary metal-oxide—semiconductors. We have contributed to oxide electronics, particularly on transition metal oxide semiconductors of which the cations include In, Zn, Sn and Ga. We have integrated these oxide semiconductors into thin film transistors (TFTs) as active channel layer in light of the unique combination of electronic and optical properties such as high carrier mobility (5-10 cm“/Vs), optical transparency in the visible regime (&gt;~90%) and mild thermal budget processing (200-400°C). In this study, we achieved four different results. The first result is that unlike several previous reports on oxide p-n junctions fabricated exploiting a thin film epitaxial growth technique (known as molecular beam epitaxy, MBE) or a high-powered laser beam process (known as pulsed laser deposition, PLD) that requires ultra-high vacuum conditions, a large amount of power, and is limited for large-area processing, we demonstrate oxide-based heterojunction p-n diodes that consist of sputter-synthesized p-SnOx and n-IGZO of which the manufacturing routes are in-line with current manufacturing requirements. The second result is that the synthesized p-SnOx films are devoid of metallic Sn phases (i.e., sn? state) with carrier density tuneability and high carrier mobility (&gt; 2 cm2/Vs). The third result is that the charge blocking performance of the metallurgical junction is significantly enhanced by the engineering of trap/defect density of n-IGZO, which is identified using photoelectron microscopy and valence band measurements. The last result is that the resulting oxide-based p-n heterojunction exhibits a high rectification ratio greater than 10° at +3 V (highest among the sputter-processed oxide junctions), a low saturation current of ~2x10 © A, and a small turnon voltage of ~0.5 V. The outcomes of the current study are expected to contribute to the development of p-type oxides and their industrial device applications such as p-n diodes of which the manufacturing routes are in-line with the current processing requirements. Reference: 1. Lee, S.; Paine, D. C., Metallization selection and the performance of amorphous In-Zn-O thin film transistors. Applied Physics Letters 2014, 104 (25), 252103. 2. Liu, M.; Kim, H.; Wang, X.; Song, H. W.; No, K.; Lee, S., Carrier Density-Tunable Work Function Buffer at the Channel/Metallization Interface for Amorphous Oxide Thin-Film Transistors. ACS Applied Electronic Materials 2021, 3 (6), 2703-2711. 3. Chu, X., Zhuang, S., Chi, C., Xu, H., Du, G., Dong, X., &amp; Yin, J. (2017). Study on the electroluminescence properties of the P-nimgo:Li/mgo/n-zno nanowires/ito heterojunction. Journal of Luminescence, 187, 486-491. 4. Kawazoe, H.; Yanagi, H.; Ueda, K.; Hosono, H., Transparent p-Type Conducting Oxides: Design and Fabrication of p-n Heterojunctions. MRS Bull. 2000, 25 (08), 28-36. 5. Mo, X., Fang, G., Long, H., Li, S., Wang, H., Chen, Z., Huang, H., Zeng, W., Zhang, Y., &amp; Pan, C. (2014). Unusual electroluminescence from n-ZnO@i-MgO core-shell nanowire color-tunable light-emitting diode at reverse bias. Phys. Chem. Chem. Phys., 16(20), 9302-9308. 6. Nomura, K.; Ohta, H.; Takagi, A.; Kamiya, T.; Hirano, M.; Hosono, H., Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors. Nature 2004, 432 (7016), 488-492.

EMC 2022

Facile Processing and Properties of P-Type SnOx and Oxide-Based p-n Heterojunction Application with n-InGaZnO

oxide electronics

p-snox

heterojunction

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021<br>
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021<br>
(on demand videos available from September 6 until November 30, 2021)

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ESSCIRC ESSDERC Educational Events

The Educational Events of ESSCIRC ESSDERC 2021. 

In recent years, oxide electronics has emerged as one of the most promising new technologies for a variety of electrical and optoelectronic applications, including next-generation displays, solar cells, batteries, and photodetectors. Oxide electronics have a lot of potential because of their high carrier mobilities and ability to be manufactured at low temperatures. However, the preponderance of oxide semiconductors is n-type oxides, limiting present applications to unipolar devices and stifling the development of oxide-based bipolar devices like p-n diodes and complementary metal-oxide—semiconductors. We have contributed to oxide electronics, particularly on transition metal oxide semiconductors of which the cations include In, Zn, Sn and Ga. We have integrated these oxide semiconductors into thin film transistors (TFTs) as active channel layer in light of the unique combination of electronic and optical properties such as high carrier mobility (5-10 cm“/Vs), optical transparency in the visible regime (>~90%) and mild thermal budget processing (200-400°C). In this study, we achieved four different results. The first result is that unlike several previous reports on oxide p-n junctions fabricated exploiting a thin film epitaxial growth technique (known as molecular beam epitaxy, MBE) or a high-powered laser beam process (known as pulsed laser deposition, PLD) that requires ultra-high vacuum conditions, a large amount of power, and is limited for large-area processing, we demonstrate oxide-based heterojunction p-n diodes that consist of sputter-synthesized p-SnOx and n-IGZO of which the manufacturing routes are in-line with current manufacturing requirements. The second result is that the synthesized p-SnOx films are devoid of metallic Sn phases (i.e., sn? state) with carrier density tuneability and high carrier mobility (> 2 cm2/Vs). The third result is that the charge blocking performance of the metallurgical junction is significantly enhanced by the engineering of trap/defect density of n-IGZO, which is identified using photoelectron microscopy and valence band measurements. The last result is that the resulting oxide-based p-n heterojunction exhibits a high rectification ratio greater than 10° at +3 V (highest among the sputter-processed oxide junctions), a low saturation current of ~2x10 © A, and a small turnon voltage of ~0.5 V. The outcomes of the current study are expected to contribute to the development of p-type oxides and their industrial device applications such as p-n diodes of which the manufacturing routes are in-line with the current processing requirements. Reference: 1. Lee, S.; Paine, D. C., Metallization selection and the performance of amorphous In-Zn-O thin film transistors. Applied Physics Letters 2014, 104 (25), 252103. 2. Liu, M.; Kim, H.; Wang, X.; Song, H. W.; No, K.; Lee, S., Carrier Density-Tunable Work Function Buffer at the Channel/Metallization Interface for Amorphous Oxide Thin-Film Transistors. ACS Applied Electronic Materials 2021, 3 (6), 2703-2711. 3. Chu, X., Zhuang, S., Chi, C., Xu, H., Du, G., Dong, X., & Yin, J. (2017). Study on the electroluminescence properties of the P-nimgo:Li/mgo/n-zno nanowires/ito heterojunction. Journal of Luminescence, 187, 486-491. 4. Kawazoe, H.; Yanagi, H.; Ueda, K.; Hosono, H., Transparent p-Type Conducting Oxides: Design and Fabrication of p-n Heterojunctions. MRS Bull. 2000, 25 (08), 28-36. 5. Mo, X., Fang, G., Long, H., Li, S., Wang, H., Chen, Z., Huang, H., Zeng, W., Zhang, Y., & Pan, C. (2014). Unusual electroluminescence from n-ZnO@i-MgO core-shell nanowire color-tunable light-emitting diode at reverse bias. Phys. Chem. Chem. Phys., 16(20), 9302-9308. 6. Nomura, K.; Ohta, H.; Takagi, A.; Kamiya, T.; Hirano, M.; Hosono, H., Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors. Nature 2004, 432 (7016), 488-492.

technical paper

After two years of virtual conferences, we're excited to host EMC 2022 in person at The Ohio State University in Columbus, Ohio. In addition to cutting-edge technical presentations given in multiple parallel sessions, opportunities to network with colleagues will be present throughout the conference. The size and format of the meeting makes networking easy, whether you have been coming to the conference for many years or are a first-time attendee.

EMC is coordinated with the Device Research Conference (DRC), which will be held the same week, from June 26-29. This recognizes the strong interaction between device and electronic materials research and provides fruitful exchange of information between attendees of both Conferences.

For information on the 80th Device Research Conference, please visit the DRC 2022 website.



The Electronic Materials Conference (EMC) is the premier annual forum on the preparation, characterization and use of electronic materials. This year’s event will feature a plenary session, topical sessions, a poster session and more.

Degradation of materials under harsh, high-temperature conditions is one of the grand challenges of high-performance energy conversion. Current approaches make use of refractory materials that do not possess ideal properties but are resistant to decomposition by heat. To suppress undesired thermal transport, multiple refractory materials are shaped and arranged with varying degrees of complexity, ranging from multilayers to plasmonic arrays and 3D photonic crystals. Ultimately these structures progress toward more thermodynamically favorable configurations and result in intermixing, reaction or new phase formation, and coarsening. This severely limits their performance in extreme conditions. Here, we introduce the concept of using immiscible refractory oxides with high crystallinity as building blocks of functional ultrahigh-temperature materials. We demonstrate epitaxial oxide heterostructures made from perovskite BaZry gHfy 593 (BZHO) and rocksalt MgO as a photonic crystal (PhC) that can suppress undesired thermal emission at a desired cutoff wavelength. The PhC is implemented as surface filter to suppress mid-infrared thermal emission from the best intrinsic, spectrally selective emitter operating at 1350°C in air. The heterostructure exhibits coherent atomic registry that retains clearly separated refractive index mismatched layers without interface coarsening, interdiffusion, phase change, or decomposition up to at least 1100°C in dry air. The use of dissimilar crystal structures, with low lattice and thermal expansion mismatch, allows for high crystallinity superlattices with interlayer immiscibility at high temperatures. The understanding gained from this study can be used to develop thermal barrier coatings and selective emitters that are resistant to instabilities in air. Beyond BZHO/MgO, we computationally identify ~10° potential oxide pairings that fit our design criteria, demonstrating the vast potential of this approach.

Control of Thermal Transport at Ultrahigh Temperatures by Immiscible Oxide Heterostructures

Among compound semiconductors, Silicon Carbide (SiC) is useful especially in the high voltage, fast switching applications. Like with all technology areas, as SiC DMOSFET technology matures in terms of performance, questions of reliability and failure take on a more central role [1]. The short circuit (SC) capability addresses a key failure mechanism in these devices. The current and the lattice temperature of the device increase tremendously with the voltage stress leading to the device burning out. Among various reasons reported for this, the conducting paths created due to the melting of contacts (Aluminum) may be considered the most important factor [1]. In this work, we investigate the effect of possible process-induced variability on SC capability by 2-D simulation. Device and Simulation Setup A generic 1200 V vertical SiC DMOSFET structure, shown in Fig. 1, is simulated in a non-isothermal environment of the TCAD platform to study the short circuit capability of the device. Thus, we have used the thermodynamic model in addition to the usual drift-diffusion for electrons and holes. The parameters for bulk and interface mobility, its degradation with temperature, and thermal parameters such as thermal conductivity and specific heat capacity have been taken from the experimental literature. The acceptor type interface trap (Qa = 1.5x10 “cm at EG EE = 0.18 eV) and oxide fixed charge density 2x10 cm ~ are defined at SIC/SIO, for the simulation. The device is normally off type, and the important parameters are tabulated in Table 1. Results We consider the variability arising from two possible processes for self-aligned channel formation. The first, illustrated in Fig. 2.a, arises from the dry etch process used to form an oxide spacer which follows the p-well implant defined by the oxide hard mask. The spacer then acts as a hard mask during the n* source region implant so as to define the channel (additive). The distance between the two p-well, in this case, is fixed. Thus, channel length variability, in this case, is towards the n’-source side ('1'). The second, illustrated in Fig. 3.a, arises from a wet etch process to move back the oxide hard mask, which is used for the n*-source implant. The shortened oxide now constitutes a hard mask for the p-well implant, and thereby defines the channel (subtractive). The distance between the two n’ -source implants, in this case, is fixed. The channel length variability, in this case, is therefore from the JFET region side (‘2’). The total cell pitch remains constant in both cases. We consider both a decrease and an increase of channel length from each side. Fig. 2.6 shows the variability of type '1', while Fig. 3.6 shows the variability of type '2'. The effect of these variability types on the SC capability is different and depends on the effective channel length, which here ranges from 0.3 to 0.7 um. For type '1', the effective channel length increases and decreases with n’ -source, and most of the other device parameters are not affected as shown in Table 1. For type '2', the varied channel length is effectively changing the JFET dimensions. The combined effect is more pronounced which can be observed from the resulting SC curves. The SC capability of the device worsens with a decrease in channel length since that leads to higher currents. The results indicate that the additive method of fabrication is preferable for the SiC-based DMOSFET for reproducible SC performance. Acknowledgement This work was supported by the IIT Bombay-Ohio State Frontier Science and Engineering Research Center under “Towards the rugged SiC technology for electric transportation” project. Reference 1. Hema Lata Rao Maddi, Susanna Yu, Shengnan Zhu, Tian-shi Liu, Limeng Shi, Minseok Kang, Diang Xing, Suvendu Nayak, Marvin H. White, and Anant K. Agarwal, “The road to a robust and affordable SiC power MOSFET technology, “Energies, vol. 14, no. 24, pp. 8283, Dec 2021.

Process-Induced Variability of SiC DMOSFET Short Circuit Capability

The role of band-tail states (BTS) on the operation of |GZO TFTs is well established, however there is wide variation in the interpretation of the interaction and/or independence of channel mobility and charge trapping. In many reports the influence of BTS on the level of free charge is accounted for by an effective mobility which is dependent on the applied gate bias. While this may accurately match current-voltage characteristics, this treatment is lumping together the effects of charge trapping and carrier scattering which should remain distinct. When these effects are combined, a model which can accurately represent device behavior over a wide temperature range is not possible due to fundamental differences in temperature dependence. Bottom-gate TFTs were fabricated with a 50 nm IGZO film sandwiched between a 50 nm gate oxide and a 50 nm passivation oxide layer. The working metal was molybdenum for the gate electrode and source/drain contacts. A passivation anneal was done and a capping layer was added to promote electrical stability; full process details are provided in a previous report. Devices were tested using a Lakeshore cryogenic probe station, with transfer characteristic measurements taken from room temperature to below 100 K. Electrical measurements made on long-channel devices (L = 12 um) has revealed temperature-dependent behavior that is not explained by existing TCAD models employed for defect states and carrier mobility. An |GZO TFT device model has been recently developed using Silvaco Atlas, which accounts for the role of donor-like oxygen vacancy defects, acceptor-like BTS, acceptor-like interface traps, and a temperature-dependent intrinsic channel mobility. The model demonstrates a remarkable match to transfer characteristics measured at T = 150 K to room temperature. The temperature-dependent mobility follows a power-law relationship, resembling behavior consistent with ionized defect scattering. The mobility model is independent of carrier concentration, without dependence on the applied gate bias. Details of the material and device model, and associated defect distribution parameters will be presented.

Separation of Defect States and Intrinsic Channel Mobility on the Electrical Operation of IGZO TFTs

Bi-containing Ill-V alloys have attracted attention over the past few decades due to their suitability for optoelectronic devices operating across a wide spectrum of the infrared region. | Integrating small amounts of Bi into Ill-V materials offers the flexibility to decrease the bandgap energy, which enables infrared emission, and increases spin orbit (SO) split band properties, which can suppress Auger recombination when larger than the bandgap energy. Current approaches for photodetector operation in the mid-wave and long-wave infrared, such as HgCdTe and InSbbased devices, suffer from large dark currents.. While nBn structures can suppress many sources of dark current, the use of AllnSb barriers in InSb-based nBn detectors result in a difficult tradeoff between undesirable valence band offset and high barrier layer strain.4 A flexible method to mitigate these challenges in InSb-based nBn detectors is to introduce small amounts of Bi and Al to InSb to tune the bandgap of InSbBi absorber regions and AllnSbBi barriers, while simultaneously minimizing strain. However, AllnSbBi remains largely underexplored, in part due to the difficulties of growing Bi-containing III-V alloys. Noteworthy are the tradeoffs in temperature and growth rate, which pose *~ In this work, material properties such as bandgap energy, lattice constant, surface morphology, and photoluminescence of AllnSbBi alloys were investigated to optimize material quality for barrier layer applications. AllnSbBi was grown by solid-source molecular beam epitaxy on n-type InSb substrates. To promote Bi incofporation, the substrate temperature was maintained around 300°C and a low VIII flux ratio of 0.975x was employed. The growth rate was chosen to be ~1 um/hr. Atomic force microscopy (AFM) and photoluminescence (PL) measurements were performed on an AllnSbBi thin film targeting ~1% Bi and ~5% Al incorporation. AFM measurements showed droplets on the film surface, however further optimization of the growth parameters may be able to mitigate droplet formation. PL measurements at 83K demonstrated that the AllnSbBi film emitted at roughly 5.1 um, whereas the AllnSb and InSbBi control films emitted at 4.9 and 5.6 um, respectively, suggesting ~0.5% Bi incorporation into AllnSb. To investigate the bandgap change with Bi incorporation, preliminary density functional theory (DFT) simulations with hybrid functionals (HSE) were performed using a 54-atom supercell with 1 Al and 1 Bi atom (corresponding to 3.7% Al and Bi). DFT predicts that the direct bandgap of Alp 037!"9.963°"0 9638/9 037 is reduced by ~20 meV from that of InSb, in qualitative agreement with the observed reduction in PL emission energy. Further growths are underway for additional alloy compositions to fill out the AllnSbBi growth space and optimize the bandgap energy, lattice constant, surface morphology, and photoluminescence to act as a barrier layer. J. J. Lee et. al., Appl. Phys. Lett. 71, (1997). L. Wang et al., Crystals 7, (2017). A. V. Voitsekhovskii and D. I. Gorn, Journ. of Comm. Tech. and Elec. 62, (2017). A. Evirgen et al., Elec. Lett. 50, (2014). M. K. Rajpalke et al., Appl. Phys. Lett. 105, (2014). S. Tixier et al., Appl. Phys. Lett. 82, (2003). R. C. White et al., 21st International Conf. on MBE, (2021).

Growth and Characterization of AlInSbBi for Wide-Bandgap Barriers on InSb

Infrared unipolar barrier detectors based on III-V materials have progressed tremendously due to success in improving material quality and bandgap engineering. In the standard nBn detector, the single unipolar barrier extends into the conduction band, blocking the majority carrier dark current and significantly inhibiting the generation-recombination and surface contributions to the dark current. The barrier serves to make the detector a minority carrier, diffusion-limited device, however doping still has a dominant impact on device performance due to its relationship with the minority carrier lifetime and minority carrier concentration. Increasing doping degrades the minority carrier lifetime, and thus the quantum efficiency of the photodetector. Diffusion dark current in the nBn detector, which is proportional to the minority carrier concentration, is initially reduced by increased doping until it begins to have an adverse effect on the minority carrier lifetime. Ultimately, absorber doping density significantly affects nBn photocollection and noise characteristics and must be precisely controlled to optimize photodetector performance. Recent advances leading to high minority carrier lifetime in strain balanced InGaAs/InAsSb superlattices have led to it being considered as a higher mobility drop-in replacement to the InAs/InAsSb superlattice nBn. Two InAs/InAsSb and three InGaAs/InAsSb nBn structures designed for maximum electron-hole wavefunction overlap with 5.1-5.3 um wavelength cutoffs have been grown with different absorber doping profiles by molecular beam epitaxy. The material is examined by time-resolved and steady-state photoluminescence, X-ray diffraction, and Nomarski surface imaging. The samples are then processed into variable-area mesa arrays using standard lithography and contact metal deposition. The devices are packaged in and wire-bonded to 68-pin leadless-chip carriers, which are then mounted in a vacuum-sealed dewar for temperature-controlled measurements of the photocurrent, dark current, and capacitancevoltage to evaluate the doping concentration profile in each device. The undoped Ga-free nBn’s exhibited the lowest background n-type majority carrier concentration of 6x10 “cm ~ with a minority carrier lifetime of 3 us. The undoped InGaAs/InAsSb superlattice exhibited a ~4« higher majority carrier concentration of 2x10 ~ cm™~ with a minority carrier lifetime of 2 us. Si-doped samples with constant and graded doping profiles are also examined, and the minority carrier lifetime is observed to degrade with increased doping. An analysis of the minority carrier lifetime’s dependance on doping, impact on detector performance and other characterization results will be presented. Approved for public release: Distribution is unlimited. AFMC PA number xxx-xxxx

Majority Carrier Concentration and Minority Carrier Lifetime in Mid-wave Infrared InGaAs/InAsSb and InAs/InAsSb Superlattice nBn Detectors

The mid-infrared wavelength range (3 -30 um, mid-IR) is a spectral range of significant importance. The mid-wave infrared (MWIR, 3 -5 um) transmission window, specifically, is vital for applications such as gas sensing and free-space communication, as well as thermal imaging of mechanical objects (engines, turbines, etc) that have temperatures ~580-970 K. For an infrared detector, efficient operation at high temperatures is typically the primary goal. While Mercury-Cadmium-Telluride (HgCdTe) detectors are the current state-of-art infrared detectors, the type-II superlattices (T2SLs) have shown to be a promising alternative material system. However, the comparatively lower absorption coefficient of the T2SL detectors presents a challenge, due to the trade-off (as a function of the absorber thickness) between large external quantum efficiency and higher collection efficiency/reduced dark current. This limitation can be addressed by incorporating thin detector absorber regions in resonant photonic architectures. One such architecture is the guided-mode resonance structure, comprising a high-refractive index grating layer sandwiched between two low-index layers[1]. Incident light diffracts into guided modes in the grating layer, which can then couple out to free space. When the outcoupled light interferes constructively/destructively with reflected/transmitted light, strong and narrow resonant peaks/dips can occur in the reflection/transmission spectra. We design a GMR structure where index-contrast required is achieved with highly doped (n**) which can be modeled with the Drude formalism, allowing for a lattice matched material system with extremely low semiconductor layers, refractive index in the MWIR, which can serve as a waveguide cladding layer. In this work, we build on our previous efforts[2], to demonstrate GMR-enhanced all-epitaxial uncooled (roomtemperature) MWIR nBn InAs/InAsSb T2SL detectors. We have designed, grown, fabricated and characterized GMR detectors showing such enhancement in a T2SL absorber only 250 nm thick. GaSb serves as a high-index grating layer which, together with the nBn detector (serving as a waveguide core), is sandwiched between a low-index n* virtual substrate and air. For grating periods A= 1.6 um and 1.8 um, resonances with enhancement of = 8x & 14 are shown at wavelengths, A= 4.4 um & 4.7 um respectively which is very close to the band-edge of the absorber (=5 um). Typically, due to the steep drop in absorption coefficient close to the band-edge, it is extremely difficult to obtain sufficient external quantum efficiency near the absorber band edge. Thus, detectors must be grown with lower energy cut-off, which will significantly increase dark current and degrade device detectivity. The ability to enhance EQE at the band edge of the absorber T2SL, allows us to use higher energy cut-off absorbers without degrading absorption efficiency. Moreover, the ultra-thin absorber, when compared to a typical MWIR detector, offers a significant reduction in dark current, when compared to traditional MWIR III-V detectors operating in same wavelength range, at similar temperatures. Significant improvement in both the optical and electrical performance of the GMR detectors results in superior specific detectivities. TE-polarized estimated specific detectivity D* = 1.2 x10 0 & 1 x19'0 cmvVHz/W are reported for the A= 1.6 um and 1.8 um devices, respectively. Future work will investigate polarization-independent detectors with substrate-side illumination for potential incorporation into focal-plane array architectures. The authors gratefully acknowledge United States Army under Prime Contract W9O09MY-20-P-0010 and National Science Foundation (ECCS-1926187 and ECCS-2025227). References: 1. S. S. Wang and R. Magnusson, Appl. Opt., vol. 32, no. 14, pp. 2606-2613, May 1993. 2. A. Kamboj, L. Nordin, P. Petluru, A. J. Muhowski, D. N. Woolf, and D. Wasserman, Appl. Phys. Lett., vol. 118, no. 20, p. 201102, 2021.

Guided-Mode Resonance Enhanced Room-Temperature Infrared Detectors

Ge has a nearly direct bandgap because the direct I valley (k = 0 in momentum space) is only 140 meV above the indirect L valley. Tensile strain (>2%) and alloying (Ge, _,Sn, or Ge, _ C_) are the two most common approaches to make Ge-based direct bandgap materials . Although Ge 4-0" becomes a direct bandgap material with x>10%, Strained growth on Ge or GaAs adds undesirable compressive strain’. Worse, the very small electron effective mass (m, = 0.02m9) loses the direct bandgap when confined in a quantum well (QW) or dot®. Our group has previously demonstrated that Ge, C. with y = 1% has a direct bandgap, and reported GeC using a special precursor (4GeMe) as a C source in molecular beam epitaxy (MBE), with no defects detected in transmission electron microscopy (TEM) ’~. In this work, we instead grew Gey ySnC using a simpler C precursor. GeSnC adds additional control in epitaxial growth: Sn and C partially compensate local strain and distortion of the host Ge bonds. Ab-initio calculations predict that C-Sn-C bonding would be energetically favorable over C-C bonds in the Ge lattice. This is likely to increase both C and Sn substitutional incorporation and provides a more stable material, similar to InGaAs:N . We saw no evidence of Sn segregation as surface droplets, nor C incorporation as undesirable C-C or C=C bonded nano-clusters. Therefore, adding Sn might reduce the carbon clustering at the surface which would be a great achievement compare with past growths by other groups. As an added benefit, GeC offers a larger electron effective mass (Mop): which would preserve the direct bandgap in GeSnC even when confined in a QW. Tensile strained Ge Sn Cy. was grown on GaAs (004) substrate in hybrid MBE using thermal Ge, Sn sources and commercial carbon tetrabromide (CBr) as the carbon source. We believe sp2 C-C pairs are likely defects in the carbon containing alloys, so we also used hydrogen to preferentially remove sp2 carbon, as is done in growth of epitaxial diamond. High resolution x-ray diffraction (HRXRD) reveals good crystallinity in the epi-layer with maximum 3% of substitutional carbon and 4% tin. Raman observation of the C local mode at 530 cm confirms substitutional incorporation into the crystal. Atomic Force Microscopy (AFM) shows mostly flat surfaces. Unlike most other carbon sources, no sp2 (graphitic) or amorphous carbon bonds were detected in Raman spectroscopy from 1200-1600 om”! (not shown). The successful incorporation of C into Ge substitutionally, without cluster carbon, is a major step toward efficient Group IV lasers for silicon photonics. We have also observed emissions in 0.50-0.60 eV range both from bulk and multiple quantum well (MQW) GeSnC samples. These peaks could be from different atomic arrangements, from defects, or from non-uniform QW compositions. The detailed origins of the emission spectrum are currently under investigation and will be reported at the conference. Reference 1. Jifeng Liu, Photonics 1 (3), 162 (2014) 2. G. Grzybowski, R. T. Beeler, L. Jiang, D. J. Smith, J. Kouvetakis, and J. Menéndez, Applied Physics Letters 101 (7), 072105 (2012) 3. M. P. Polak, P. Scharoch, and R. Kudrawiec, Journal of Physics D: Applied Physics 50 (19) (2017) 4. C. A. Stephenson, W. A. O'Brien, M. W. Penninger, W. F. Schneider, M. GillettKunnath, J. Zajicek, K. M. Yu, R. Kudrawiec, R. A. Stillwell, and M. A. Wistey, Journal of Applied Physics 120 (5) (2016) 5. C. A. Stephenson, W. A. O'Brien, M. W. Penninger, W. F. Schneider, M. Gillett-Kunnath, J. Zajicek, K. M. Yu, R. Kudrawiec, R. A. Stillwell, and M. A. Wistey, Journal of Applied Physics 120 (5) (2016). 6. Vincenzo Lordi, Homan B. Yuen, Seth R. Bank, Mark A. Wistey, James S. Harris, and Stephan Friedrich, Physical Review B 71 (12) (2005)

Molecular Beam Epitaxy Growth of Highly Tensile Strained GeSnC Alloys up to 4% Sn and 3% C

Ill-Nitride light emitting diodes have been successfully adopted in visible display and illumination applications, and are very promising for ultra-violet wavelength applications. Tunnel junctions can provide several significant advantages for operation of both visible (for multiple active region LEDs) and UV LEDs (to act as transparent spreading layers). Recent work on tunnel junctions have demonstrated excellent characteristics for both GaN, as well as ultra-wide bandgap AlGaN. Although tunnel junctions (TJs) have been demonstrated with excellent electrical efficiency, and low voltage drop, especially for GaN-based LEDs, the absorption introduced by them has not been well-understood. Design of tunnel junctions for low voltage drop often requires the use of ultra-thin layers of lower bandgap material (such as InGaN) which could have substantial absorption at emission wavelengths. Previously used methods to calculate tunnel junction absorption losses, such as ray tracing and finite-difference time-domain FDTD [1] do not take into account photon recycling in the TJ. In this work we propose a theoretical model that can provide an intuitive understanding of the impact of photon recycling on the optical absorption losses in tunnel junctionbased LEDs. The proposed model is derived using a 1-dimensional N-cascaded GaN LED structure. The top metal contact is considered as a perfect reflector, and the output optical power is collected at the bottom side. GaN layers are assumed to be transparent, while any power absorbed by the TJ is recycled by generating an electron-hole pair (EHP) that is injected back to the active region to recombine there. The efficiency, n , by which the generated EHPs produce new photons in the active region is assumed to be the mathematical product of the IQE and the injection efficiency. The proposed closed form model takes into account the infinitely repeated photon recycling process. The model enables an estimate of the normalized light extraction efficiency, and can be compared with estimates from simple ray tracing model single and cascaded multiple active region TJ LEDs. It is shown that as the number of TJs increases and/or its absorption increases, the recycled power increases. Consequently, while ray tracing models would predict significant absorption losses, taking into account photon recycling shows that the effective loss is significantly lower. The model can also describe the impact of the internal quantum efficiency on the effective light extraction efficiency. For InGaN polarization engineered TJs, a comparison between the two models at various Indium compositions and thicknesses shows that for Ng 94F8q 76 N TJ LED, ray tracing model predicts absorption losses that are significantly higher. For example, for 3 nm 24% In-content tunnel junction, the ray tracing model predicts total absorption loss of 7.95%, whereas the loss including the photon recycling is only 2.94%. In summary, our work shows that absorption effects in tunnel junctions can be significantly overestimated if photon recycling is not taken into account. The work presented enables rational design of tunnel-junction based LEDs with accurate estimation of absorption losses. References: [1] L. and C. M. and W. C. Lalau Keraly C. and Kuritzky, “Light Extraction Efficiency Part A. Ray Tracing for Light Extraction Efficiency (LEE) Modeling in Nitride LEDs,” in III-Nitride Based Light Emitting Diodes and Applications, J. and A. H. and M. H. Seong Tae-Yeon and Han, Ed. Dordrecht: Springer Netherlands, 2013, pp. 231-269. doi: 10.1007/978-94-007-5863-6_9.

Impact of Photon Recycling on Absorption Losses in Tunnel Junction-Based III-Nitride LEDs

It was both theoretically and experimentally proved that the growth of In Ga 4-xN quantum wells (QWs) on In Ga,_ N underlayer (x > y) would significantly improve the light emitting diodes (LEDs) performance, attributing to the reduction of non-radiative recombination centers, the decline of the internal electrostatic field, and the improvement of indium composition uniformity in QWs. Moreover, the reduced lattice mismatch between QWs and underlayer greatly suppresses composition pulling effect, which improves indium incorporation rate grown at the same temperature, resulting in In-rich InGaN with highly crystalline. However, to serve as templates for red emission QWs, a thicker InGaN pseudo-substrate with closer indium mole fraction to QWs grown beyond the critical layer thickness is desired. In this work, we present an approach to achieve a sub-micron size InGaN underlayer with high to 30 % indium composition, while the thickness is around 90 nm, far exceeding the critical layer thickness of such In-rich InGaN layer on planar c-plane GaN (reported less than 5 nm). The InGaN platelet is demonstrated by selective area growth (SAG) on arrays of GaN seed from circle openings with a diameter of 400 nm ina SiN, mask. To our best knowledge, SAG of InGaN results in random nucleation and uneven shape due to the low diffusion length of gallium precursor at relatively low growth temperature. It was reported that the selectivity of InGaN can be enhanced by introducing pyramid shaped GaN seed first, resulting in InGaN pyramid. However, the local indium composition fluctuation on the semipolar facet of the InGaN pyramid hinders pure red emission of QWs with small full width at half maximum (FWHM). In this work, planar hexagonal shape of GaN seed was introduced first before SAG of InGaN, leading to the formation of uniform InGaN platelets with c-plane domain morphology. The optical properties of the InGaN platelets were characterized by photoluminescence (PL, excited by a He-Cd laser of 325 nm, 15 mW, room-temperature), showing PL peaks around 530 nm with FWHM of 141 meV, suggesting around 30 % indium incorporated. AFM scan of the top c-plane surface of the InGaN platelet indicates an atomically flat surface without v-pits or trench defects while the thickness is over 90 nm. Cross-sectional TEM characterization of InGaN platelet suggests homogenous crystalline and shape interface between InGaN and GaN seed. According to localized EDX line measurements recorded with the same area, the InGaN platelet shows indium composition almost linearly increased from InGaN/GaN interface to c-plane surface. Detailed line profiles show indium composition of 25 % to 30 % at the top surface and 15 % to 20 % at InNGaN/GaN interface. Such high indium-content InGaN platelets are competitive candidates for the development of high-quality yellow-to-red emission InGaN micro-LED, by increasing the indium incorporation rate and reducing the lattice mismatch for later Inrich quantum wells.

High In-Content InGaN Platelets as Underlayer for Light-Emitting Diodes Toward Long Wavelength Application

This abstract explores the possibility of employing metal additive microfabrication of system in package (SiP) with inbuilt heat sinks and leadframe consisting of multiple pads for QFN packaging. The SiPs were fabricated using 17-4Ph stainless steel powder employing a relatively less expensive DMLS system. The use of affordable metal additive manufacturing systems is considered by the authors to encourage further research on its applicability towards heterogenous integration in the semiconductor industries. The International Technology Roadmap for Semiconductors (IRTD) 2012 emphasized on the importance of integration of system on chip (SoC) and SiP. DMLS is one possibility for such heterogenous integration due to the possibility of customization as the parts are directly fabricated from a CAD file. DMLS has been considered superior to its plastic or resin-based counterparts in applications where conductive parts with better accuracy and strength are required. All these features make DMLS parts, a possible option for the fabrication of SiP with few functionalities like heat sinks and connectivity. 3D packaging and heat extraction for die is one of the grand challenges of International Roadmap for Devices and Systems (IRDS). In this abstract, different QFN leadframes with and without cooling systems are presented. The original leadframe design with only the pads forms a comparison reference for the remaining three systems. The three systems are: QFN leadframe with microchannel, inlet, and outlet for fluid flow, QFN leadframe with arrays of fins below the die location, and a QFN leadframe with fins along with additional inlet and outlet for optional fluid flow. Figure 1 shows the CAD top views of all four proposed package system. Each package system can hold a 1cm by 1cm semiconductor die for testing purposes. The microchannels are 500um square channels whereas the fins are 1000um in diameter. The affordability comes with the trade-off of resolution and the present DMLS system can faithfully produce the mentioned dimensions with compatible features for the channels and fins. The first step towards the fabrication of the packages is the CAD design and simulation. The CAD design was then fed to the metal 3D printer, which then sliced the model and created 3D laser part. The fabrication proceeds by melting and fusing a 30um layer of powder, repeating the process, creating layers on top of layers, and fusing them together until the final 3D part is built as per the CAD file. EDM wire cutting or grinding of previously created support structure could be used to separate the parts from the build plate. Figure 2 shows the steps involved in fabrication. On each separate parts, 1cm by 1cm semiconductor dies (all same) are carefully placed. Wire bonding will be used to connect the via to the leadframe pads and inlets/outlets will be extended. The whole system will then be covered with epoxy and left to cure. The final step will be to grind away the back end of the cured part to remove support metal plate on the bottom of the packaging parts as shown in Figure 3. Figure 4 shows the separated parts with a spot for semiconductor die to be affixed and various other sub-parts. Figure 5 shows the water (colored for visibility) filled leadframe with microchannel, and the other one with fins, inlet, and outlet is shown in Figure 6. Figure 7 shows the preliminary infra-red image of all four devices heated to 40°C and left to cool down. The devices were in the same order as Figure 4. As per the theoretical idea, fins with channels performs the best followed by the one with microchannel, and the one with only fins based on the time required for them to cool down (a-f in Figure 4). The preliminary result appears promising and the material characterization along with testing is in process. Figure 8 and 9 shows the SEM characterization of build device compared to the design. The variation from the design is very small.

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