United States

This paper is demonstrating for the first time a full, industrial-grade, DFT-based approach in 22FDX node combining PVT and Aging compensation, with runtime test solution for hard events detection (TDDB, EMG,..) and Fail Operational mode for compliance with 2018 version of ISO26262 norm

IRPS 2022 Main Conference 

Runtime Test Solution for Adaptive Aging Compensation and Fail Operational Safety mode

It is my great pleasure and honor to welcome you to the 64th Annual Meeting of the Association for Computational Linguistics (ACL 2026), held in San Diego, California, USA, July 2–7, 2026. ACL 2026 continues our fields tradition of excellence in scholarship, innovation, and inclusivity, and I am deeply grateful to the many volunteers who have worked tirelessly to bring this event to life.

It is exciting to see the many developments in the field reflected at our conference, such as the advancement of large language models (born out of our community) into many application directions. This is not without challenges, partly due to unsolved problems, and partly due to misuse of the technology. All this is reflected well at ACL 2026. The conference also reflects that the field is not only about advancing technology, but also the science of fundamentally understanding language and how it is use by many different speaker communities. 
[Full Message from General Chair Philipp Koehn](https://drive.google.com/file/d/1QiJFOmMjvDgsDo3i1XzlQnImxe3RU_Cy/view?usp=sharing) 
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ACL 2026

The 64th Annual Meeting of the Association for Computational Linguistics (ACL 2026) will take place in San Diego, California, from July 2 - 7, 2026.

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#### Welcome to the 60th IEEE International Reliability Physics Symposium (IRPS)!

[![](https://assets.underline.io/uploads/markdown_image/1/image/f6b8cf9ecca2209dd3e0fcebe80a2915.png)](https://underline.io/events/282/reception) [![](https://assets.underline.io/uploads/markdown_image/1/image/e787ff477f8d2b687fb0b54d83d35e11.png)](https://drive.google.com/drive/folders/1GAycr7pPrZG2ZzZP-geUL8vGWswjCB1N?usp=sharing) [![](https://assets.underline.io/uploads/markdown_image/1/image/7492fafcc0c623afe96fe15207855ed9.png)](https://www.irps.org/)
 

**General Chair Welcome Message**

Welcome to IRPS 2022! When the IRPS Management Committee began making plans for Dallas, we recognized the strong desire by the reliability physics community to return to a face-to-face symposium that we last had in Monterey in 2019. But as time progressed, we recognized that travel restrictions were not being lifted as rapidly as we anticipated. Rather than leave out those of you who could not attend in person, we adopted a hybrid format allowing for both remote attendance and remote presentations. This is a first for IRPS and I am confident it will be a success for all.

With this new hybrid format, the symposium will return to the original five-day format with Tutorials and Year in Review on the first two days. The Technical Program, Keynote Talks, Workshops and Poster session will be held on the following three days. All of these (except Workshops and Posters) will be available via real-time streaming in the US Central Time zone with virtual attendees having Q&A access to the presenters. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees for a month after the symposium with the ability to communicate with the authors.

In 2020, we were planning on co-hosting the International ESD Workshop (IEW) ESD workshop when the COVID-19 pandemic hit. For 2022, IEW will be seamlessly embedded into the IRPS Program and will sponsor three tutorials, an invited talk, two technical sessions and two evening workshops focused on ESD and latch-up. And we continue our
collaboration with our sister conference, European Symposium on Reliability of Electron Devices Failure Physics and Analysis (ESREF) by hosting their Best Paper and the International Integrated Reliability Workshop (IIRW) by hosting their Best Student Paper.

Our primary objective is to maintain the symposium’s leadership role in the reliability physics of microelectronic devices by attracting leading researchers to present their work and providing attendees the best place to access this information. With all the buzz in the media about whether Moore’s Law has hit its limit, IRPS has been promoting expertise developed in silicon-based reliability over the past sixty years and expanding into new material areas. This year, eight of the technical sessions are devoted to reliability in topics outside of traditional silicon, including wide bandgap GaN/SiC, emerging memory and neuromorphic computing. I hope our ability to draw these communities together will accelerate the cross-fertilization of ideas. 

The Technical Program consists of four keynote speakers, twenty-three invited speakers and eighty-seven oral presentations organized in thirty technical sessions on eighteen reliability topics. Over two evenings, there will be ten Workshops and sixty-six Poster presentations that are designed to allow in person attendees and experts to interact
with one another. With eighteen tutorials covering topics ranging from fundamental transistor and memory reliability all the way up to automotive and complex system-level reliability, this year’s symposium provides an excellent learning opportunity for engineers and scientists new to reliability as well as experienced individuals wanting to explore new
areas. The Year in Review, which serves as a summary of research in the past year, will cover 3D packaging, emerging memory and aging aware circuit designs.

Finally, I would like to express my extreme gratitude to our patrons and exhibitors, whose support makes IRPS possible.
And to all of you, our in person and virtual attendees, for supporting this symposium for sixty years!

**Charles W. Slayman, General Chair** 
**of 2022 IRPS Management Committee**
 
**About IRPS**

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

n advanced technology, the effect of self-heating (SH) on hot-carrier degradation (HCD) activation energy (Ea) has been studied by temperature correction under DC stress but frequency dependance of HCD under AC condition is discussed thoroughly. In this study, it is experimentally observed that after considering the influence of SH, device lifetime still increases with shorter stress pulse width. Based on these experimental results, a universal HCD model is proposed which could cover both DC and AC stress waveforms with different pulse width (pstress).

Universal Hot Carrier Degradation Model under DC and AC Stress

We report preliminary results on bias temperature instabilities (BTI) on 28FDSOI MOS transistors from 300K to 4K. Common models describe BTI as a temperature-activated effect, which is suppressed at cryogenic temperature. Our measurements show that some BTI remains even at 4K, underlying another degradation mechanism, and we offer insight into the characteristic temperature and time scales. We show that the back-gate voltage can be used to mitigate BTI degradations. An anomalous signal is observed in small PMOS, which can be caused by trapping from the gate.

Fast Measurement of BTI on 28nm Fully Depleted Silicon-On-Insulator MOSFETs at Cryogenic Temperature down to 4K

The root causes for the anomalous Pf-tf scaling behavior in the adiabatic regime are identified for a BiCMOS-based ESD protection for the first time. TCAD is used both to understand the turn-on of the integrated architecture with two coupled bipolar transistors under different ESD pulses and to explore the main physical mechanisms leading to the thermal runaway and failure. Simulations clearly show the complex interaction between the conductance modulation and the onset of hot spots in the full volume of the device structure, leading to the identification of critical parameters for the optimization of the proposed ESD cell.

TCAD investigation of Power-to-Failure evaluation for ultrafast events in BJT-based ESD protection cells

Periphery pFETs fabricated with the sub-20nm technology are investigated under hot carrier stress conditions when the gate voltage (|Vg|) is lower than the drain voltage (|Vd|). Two types of defects are identified: the donor-like interface trap generation causes the positive charge formation while the electron trapping in oxide traps leads to the negative charge accumulation. The corresponding energy and spatial locations are identified by analyzing the defect-induced mobility degradation and the recovery characteristic. Finally, a defect-based model is proposed for both the threshold voltage shift and the mobility degradation, which allows the prediction of the full IV after aging. This work paves a new avenue to develop accurate reliability model of periphery pFETs, a prerequisite for future device/circuit co-optimization in DRAM peripheral circuits.

Characterization and Modelling of Hot Carrier Degradation in pFETs under Vd>Vg Condition for sub-20nm DRAM Technologies

The first experimental study of floating-body characteristics for both n- and p-channel devices is demonstrated using the vertical gate-all-around split-gate Flash with channel diameter around 60nm. The maximal Vt shifts are around ~0.38V and 0.32V for n- and p-channel devices, respectively. The retention is ~80usec for n-channel devices, but is extended to nearly 10msec for p-channel devices. 3D TCAD model was established to comprehend the FBC of the vertical split-gate GAA structure. This work suggests the transient charge storage in large GAA diameter. For ordinary Flash memory or LOGIC operations, the aggressive scaled GAA diameter can avoid transient FBC effects.


First Experimental Study of Floating-Body Cell Transient Reliability Characteristics of Both N- and P-Channel Vertical Gate-All-Around Devices with Split-Gate Structures

This paper presents thermal-neutron soft error rates (tnSER) in 7 nm bulk-FinFET technology with applied Cobalt (Co) contact. A thermal-neutron irradiation test at MURR shows tnSER reduction in the 7 nm: the tnSER in the 7 nm (Co-contact) is 0.0012X of the tnSER in 14 nm (Tungsten (W)-contact). Simulation analysis shows that tnSER changed by 0.21X due to the advancement of transistor technology (from 14nm to 7nm) and 0.0057X due to the change in contact-material (from W to Co).




Thermal-Neutron SER Mitigation by Cobalt-Contact in 7 nm Bulk-FinFET Technology

Soft error rates (SER) are characterized for the 5-nm bulk FinFET D flip-flops for alpha particles, thermal neutrons, and high-energy neutrons as a function of supply voltage. At nominal operating voltage, the 5-nm node has higher SER than the 7‑nm node for all three particle types, with increases of 148%, 168%, and 26%, respectively. The overall SER for the 5-nm node was ~2X greater than that of the 7-nm node, because the reduction in critical charge was higher than that in collected charge. For alpha particle exposures, temperature effects on SER were more prominent for the 5-nm node than both the 7‑nm and 16-nm node. Relative contribution of alpha particle SER increases with scaling, and it accounts for 13% of the overall SER at the 5-nm node. 

Soft Error Characterization for 5-nm Bulk FinFET Technology in Terrestrial Enviroment

Finfet technology will not be able to keep up with the transistor scaling needs. The development of new transistor architectures, such as nano-wire and nono-sheet transistors are being pursued. Lack of short-channel control results in higher transistor Ioff per unit device width. Combining with more transistors packed in a mm2 Si area and higher Ioff/um, total product standby leakage/cm2 tends to increase with scaling. In addition, the maximum Vdd_stress is getting lower as the design rules are scaled down and the lower-K dielectrics are employed. Higher standby leakage could limit the temperature and voltage that can be used in HTOL testing. HTOL testing strategy in complex SOCs will be presented.
In terms of the reliability of intrinsic core transistors, transistor speed aging and mismatch degradation negatively impact Vmin shift of core logic and memory circuits. For the I/O circuits, lower voltage use at a higher speed demands the use of advanced process nodes, bringing many challenges to circuit design and qualification methodology. A suitable assessment methodology must be implemented to cover reliability weakness of the I/O interfaces. The challenges in reliability qualification testing of ICs will be presented.
In order to meet thermal performance and form factor, IC packaging technology is continuously evolving. These changes can lead to lower solder joint reliability of advanced IC packages. Understanding the mechanical and thermal interaction of new packages with the system board is becoming more important. Both Finite Element Analysis (FEA) and experimental data will be presented to address this critical reliability challenge.


Reliability qualification challenges of SOCs in advanced CMOS process nodes

This paper provides a summary of most recent advances and trends in automotive safety, especially related to Automated Driving Systems (ADS). It covers both functional safety, safety of the intended functionality (SOTIF) and their relationships with other areas of dependability such as cybersecurity. It also covers the several standardization activities currently ongoing in safety and Artificial Intelligence. The paper mostly focuses on HW but it also describes the major challenges related to HW-SW interface.

Recent advances and trends on automotive safety

In this work we compared AC and DC bias temperature instability (BTI) degradations induced by stressing the channel and Junction-FET regions in 4H polytype n-channel Silicon Carbide (SiC) based power MOSFETs. We observed that the degradation caused by AC BTI stress is dependent on the device technology generation unlike the DC BTI stress degradation, which is found to be independent of technology generation. Also, we found that the AC BTI stress causes more permanent damage to the device due to the creation of interface traps and border traps in contrast to DC BTI where only border traps are responsible for the degradation. 

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Universal Hot Carrier Degradation Model under DC and AC Stress

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