Italy

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9299.pdf

**Abstract:**

In this paper, we propose an in-memory True Random Number Generator (TRNG) using Voltage-Controlled MRAM that doesn’t require calibration of the writing pulse’s width and amplitude. Previous solution using Spin Transfer Torque (STT) MRAM requires calibration for every MTJ, thus making the multi-row random number generation inside the memory impossible. We also propose a 100% relative throughput digital bias correction circuit that doesn’t degrade bit rate. The VC-MTJs are fabricated in CMOS BEOL compatible process with an 80 nm diameter and high TMR ratio of 160%. MRAM array circuits and bias correction circuits are fabricated in 65 nm CMOS technology and wire-bonded with the VC-MTJ devices. Multiple VC-MTJs are tested and shown to pass all NIST randomness tests.

ESSCIRC ESSDERC 2021

A Calibration-Free In-Memory True Random Number Generator Using Voltage-Controlled MRAM

random number generator

memory

security

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INTERMAG 2021

technical paper

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





**Please read the paper on the following link:**

https://1worldcontent.com/ess/9053.pdf

**Abstract:**

This paper presents an all-paths inductor-connected buck-converter (APICBC). The APICBC balances conduction losses and has continuous paths-currents for high-frequency switching. Efficiency is optimized over a wide load current range due to the adaptive sizing of the power transistors. The converter has three inductors implemented by bond-wire and PCB patterns and operates with a switching frequency of 100 MHz. The maximum efficiency is 81.2%, and the IC is implemented in a 0.18 μm CMOS process.

A 100-MHz 81.2% All-Paths Inductor-Connected Buck-Converter with Balanced Conduction-Losses and Continuous Path-Currents

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9129.pdf

**Abstract:**

This paper demonstrates complementary 2-D FETs based on molybdenum disulfide, Mos₂, as the active film. The n-type (n-FET) and p-type (p-FET) characteristics are obtained from undoped and Nb-doped Mos₂, respectively. We have achieved similar output current drives and high on-off current ratios of more than 10^6 for both devices. Based on the proposed Mos₂ FET technology, a complementary metal-oxide-semiconductor (CMOS) inverter circuit with a gain of around 20 and 85% total noise margin at a 3 V supply, is integrated, exhibiting the potential of the proposed technology for thin film applications such as in flexible electronic circuits.

Complementary Two-Dimensional (2-D) MoS₂ FET Technology

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9281.pdf

**Abstract:**

In this work, experimental assessment of the variability of threshold voltage and drain current in junctionless nanowire nMOS transistors is presented. Die-to-die variability of threshold voltage and drain current is presented and compared to inversion mode nanowire with the same dimensions. Although the junctionless nanowires have shown larger threshold voltage matching coefficients than inversion mode devices, the variability obtained experimentally has shown to be smaller than predicted by some simulations reported in the literature. Also, it has been shown that as the channel length of junctionless nanowire transistors is reduced, the current variability becomes smaller than in inversion mode nanowires, at the same current level and dimensions.

Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9078.pdf

**Abstract:**

The improvement of forming gas anneal (10 % H2 in N2) at 400 °C on electrical properties of Ge/GeOx/Tm2O3/HfO2 gate stacks is investigated. It is found that forming gas anneal effectively suppresses fixed charge density, oxide trap density and interface state density. Hydrogen is demonstrated to efficiently passivate the negative fixed charge density and reduce the global variability of the flatband voltage down to 90 mV over a wafer. A forming gas anneal is also found to reduce equivalent oxide thickness in scaled gate stacks.

Improvement on Ge/GeOx/Tm2O3/HfO2 Gate Performance by Forming Gas Anneal

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9069.pdf

**Abstract:**

This paper discusses the effect of back-end of line (BEOL) process on cell performance for a Phase-Change Memory embedded in a 28nm FD-SOI platform (ePCM). The impact of BEOL is first shown by describing the microscopic evolution of the active Ge-rich GST alloy during process. Ge clustering has been proven to occur during the fabrication process, impacting the pristine resistance and the after forming cell performance. Two different BEOL processes are then benchmarked in terms of key performance. An optimized process is then identified, and an extensive electrical characterization of array performance and reliability is performed on the full 16MB chip. The optimized BEOL process results in a memory cell fully compatible with the requirements for demanding automotive applications.

Improving Ge-rich GST ePCM Reliability Through BEOL Engineering

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9256.pdf

**Abstract:**

This paper presents a single-chip high-voltage transceiver ASIC for low-ﬁeld NMR spectroscopy. The chip integrates an adjustable high-voltage (HV) H-bridge power ampliﬁer (PA) with a PLL frequency synthesizer and a quadrature low intermediate frequency (low-IF) receiver, achieving a measured input-referred voltage noise density of 1.1 nV/√Hz. The operating frequency of the chip is from 0.1 MHz to 200 MHz, supporting all relevant Larmor frequencies for low-ﬁeld mobile and portable NMR. The PA consists of four isolated 50 V NMOS transistors, isolated gate drivers with a digitally adjustable deadtime control, high-frequency level shifters, and a TX-control logic that supports bootstrapping of the integrated high-side drivers. The output current can be deﬁned by an adjustable voltage supply from 0 V to 50 V, delivering a maximum current of 2.0 A_pp into a non-tuned 3 mm NMR coil and up to 8.3 A_pp into a parallel tuned NMR coil. Inside a custom-designed 1.1 T portable NMR magnet, the system achieves a spin sensitivity of 1.1 × 10^16 spins/√Hz and a concentration sensitivity of 1 mM/√Hz.

A 0.1 MHz to 200 MHz High-Voltage CMOS Transceiver for Portable NMR Systems with a Maximum Output Current of 2.0 App

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9211.pdf

**Abstract:**

We present a tunneling magnetoresistive (TMR) sensing microsystem consisting of a low flicker noise TMR sensor and a custom integrated readout frontend. The proposed sensor readout circuit introduces a novel ultra-low-noise current biasing scheme for the TMR sensor, which achieves a very low current noise floor of 2.2 pA/sqrt(Hz) for a 1mA biasing current. The TMR output voltage is processed by a differential readout scheme to improve the baseline-to-signal ratio. The microsystem also features an on-chip 10-bit current DAC that allows compensating for the large process variations in the TMR base resistance value. The readout chip is manufactured in a 180nm SOI CMOS technology and heterogeneously integrated with the TMR sensor. The readout chain provides a thermal noise floor of 4 nV/sqrt(Hz), while, together with the biasing scheme, consuming a total power of 38mW. The complete sensor system consisting of the TMR and the readout circuit provides a state-of-the-art magnetic field noise floor of 120 pT/sqrt(Hz).

A Readout Circuit for Tunnel Magnetoresistive Sensors Employing an Ultra-Low-Noise Current Source

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9201.pdf

**Abstract:**

This paper introduces a new architecture of a discrete-time charge-rotating low-pass filter (LPF) which achieves a high-order of filtering and improves its stop-band rejection while maintaining a reasonable duty cycle of the main clock at 20%. Its key innovation is a linear interpolation within the charge-accumulation operation. Fabricated in 28-nm CMOS, the proposed IIR LPF demonstrates a 1--9.9 MHz bandwidth programmability and achieves a record-high 120 dB stop-band rejection at 100 MHz while consuming merely 0.92 mW. The in/out-of-band IIP3 is +18.6/+26.6 dBm.

A Charge-Rotating IIR Filter with Linear Interpolation and High Stop-Band Rejection

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9190.pdf

**Abstract:**

This paper presents the design and the validation of a continuous-time 2nd-order analog filter with 40 MHz -3 dB cut-off frequency. The circuit synthesizes a pair of conjugated complex poles by leveraging the inductive behaviour of the source node of the folded branch of a differential amplifier. This circuital technique dominates noise power and harmonic distortion by a simple input MOS transistor pair of a differential stage, resulting in 7-nV/√Hz in-band Input Referred Noise power spectral density and 69 dB output Dynamic Range. Moreover, this solution enables the introduction of gain in the filter, relaxing gain, power, and bandwidth requirements of the following stages in cascade structure. A filter prototype is realized in 28 nm CMOS, consuming 309 µW from 1.1 V and performing –6 dBm in-band Input IP3 at 20 dB passband gain.

309-µW 40-MHz 20-dB-Gain Analog Filter in 28nm-CMOS

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9089.pdf

**Abstract:**

This work introduces a class of voltage references able to operate down to 3.2 pW and 0.2-V supply for energy harvesting with relaxed or suppressed voltage regulation (direct harvesting). Inherent wafer-to-wafer process sensitivity limitations and effect of process corners in deep sub-threshold are mitigated via a selection/combination of circuit replicas driven by a process sensor, at zero testing effort and trimming. A 180-nm testchip shows 1.6% process sensitivity (including wafer-to-wafer variations), 60.7-µV/V line sensitivity, and 34.9-µV/°C temperature coefficient, leading to 1.4-mV overall accuracy across corner wafers.

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