Italy

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9117.pdf

**Abstract:**

Shunt admittance of FETs for mm-wave switch applications are investigated, complementing the well-know series elements Ron/Coff. Tese shunt elements can be responsible for significant loss, and devices with the lowest RonCoff may not be the best suited for high-frequency switches. This is demonstrated by comparing 20 nm SLVT and BFMOAT devices from GLOBALFOUNDRIES’ 22FDX® technology. While the SLVT presents an RonCoff metric of 100 fs, it is outperformed by the BFMOAT that has an RonCoff of 160 fs, thanks to reduced parasitic shunt loss. A DC-80 GHz SPDT is measured, showcasing BFMOAT’s excellent characteristics for mm-wave switches, achieving competitive results.

ESSCIRC ESSDERC 2021

Impact of Device Shunt Loss on DC-80 GHz SPDT in 22 nm FD-SOI

utbb

5g front-end

millimeter-wave ic

ultra-wideband

switch

shunt parasitic loss

roncoff

fd-soi

spdt

**[DOWNLOAD THE DRC 2021 DIGEST](https://drive.google.com/file/d/17_-pkYf4IBbVuNYgohTf0iZJORVGp_uN/view?usp=sharing)**

**[DOWNLOAD A COPY OF THE FINAL DRC PROGRAM](https://drive.google.com/file/d/1Ek8UIDCowpLq0z2hXav5tn67FboxS03N/view?usp=sharing)**

For almost eight decades, the Device Research Conference (DRC) has brought together leading scientists, researchers and students to share their latest discoveries in device science, technology and modeling. Notably, many of the first public disclosures of key device technologies were made at the DRC. This year marks the 79th anniversary of the DRC—the longest running device research meeting in the world. As we commemorate this meeting, the high-caliber technical sessions will be highlighted by plenary talks and invited talks by international research pioneers and leaders behind modern electronic technology.

Given the ongoing global health concerns associated with COVID-19 (Coronavirus), the DRC leadership has decided to hold the 2021 Device Research Conference in a virtual (online) format. This follows an enormously successful 2020 DRC held virtually, in which we had record attendance and worldwide participation of more than 875 attendees from 33 countries.

The 2021 Conference will feature:

* Informative, timely short courses in rapidly developing fields
* Oral and poster presentations on electronic/photonic device experiments and simulations
* Plenary and invited presentations given by worldwide leaders
* Evening “rump” session
* Strong student participation and Student Paper Awards

DRC is held in coordination with the Electronic Materials Conference (EMC), which will occur the same week, from June 23-25. As has happened in person in past years, in 2021, the virtual DRC and EMC sessions on the shared day, Wednesday, June 23, will be open to all attendees from both conferences. This recognizes the strong interaction between device and electronic materials research and provides fruitful exchanges of information between attendees of both Conferences. For information on the 63rd Electronic Materials Conference, please visit the [EMC 2021 website.](https://www.mrs.org/63rd-emc/)

2021 DRC individual presentation videos will become available in Underline at the end of each technical session. A recording of each full live session with Q&A will be posted later during the conference. To facilitate re-viewing of recorded talks and sessions, the DRC Underline site will remain open through 11:59pm (US EDT) on July 7th. DRC Conference registration will remain open at www.mrs.org/drc-2021/registration through June 30th.

Thank you for joining us at the 2021 Device Research Conference!

**General Chair**
 Zhihong Chen, Purdue University

**Technical Program Chair**
 Becky (R.L.) Peterson, University of Michigan

**Technical Program Vice-Chair**
 Gregg Jessen, BAE Systems

You can register for the 79th Device Research Conference with the following link. https://www.mrs.org/drc-2021

DRC 2021

For almost eight decades, the Device Research Conference (DRC) has brought together leading scientists, researchers and students to share their latest discoveries in device science, technology and modeling. Notably, many of the first public disclosures of key device technologies were made at the DRC. This year marks the 79th anniversary of the DRC—the longest running device research meeting in the world. As we commemorate this meeting, the high-caliber technical sessions will be highlighted by plenary talks and invited talks by international research pioneers and leaders behind modern electronic technology.

technical paper

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9199903

**Abstract:**

In this paper, a broad-purpose compute-inmemory solution (±CIM) able to handle arbitrary sign in both inputs/features and weights/coefficients is introduced. The ability to operate on arbitrary sign and under variable precision on both operands enables a wide range of applications, ranging from conventional neural networks to digital signal processing and monitoring. The ±CIM pipelined architecture, the reconfigurable row encoder and the adoption of a commercial 2-port bitcell allow uninterrupted memory availability for conventional read/write, even when performing in-memory computations.

Broad-Purpose In-Memory Computing for Signal Monitoring and Machine Learning Workloads

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9491142

**Abstract:**

Time-domain computing-in-memory (TD-CIM) architectures have three challenges for accelerating multi-bit DNNs due to their inferior bit-split convolution: poor network adaptability, massive redundant computations, and high quantization energy and error. This work firstly proposes a unique-weight kernel decomposition based convolution method for accelerating multi-bit DNNs. Then a TD-CIM based processor is designed with three techniques to address above challenges: 1) Cross-flipping based kernel decomposer to reduce memory accesses, 2) Dual-mode complementary predictor to remove redundant computations, 3) Activation-weight-adaptive pulse quantizer to reduce quantization energy and error. Fabricated in 28nm and evaluated with 1-to-8bit DNN, the processor achieves 2.4-to-152.7TOPS/W peak energy efficiency.

A Time-Domain Computing-in-Memory Based Processor Using Predictable Decomposed Convolution for Arbitrary Quantized DNNs

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9203868

**Abstract:**

A 6.4 nW 1.7 % relative inaccuracy (R-IA) CMOS sub-thermal drain voltage-based temperature sensor is proposed. The proposed stabilized sub-thermal drain voltage current generator achieves a highly linear PTAT output without nonlinearity fitting or post-fabrication trimming, and increases the accuracy of the sensor. The combination of the current generator and a frequency-locked-loop relaxes the tradeoff between power and temperature stability of the current-to-frequency converter, and achieves supply-voltage-independent operation. Measured results of the prototype fabricated in a 65 nm CMOS process show that the proposed temperature sensor has a -1.0/+0.7 °C inaccuracy (= R-IA of 1.7 %) while achieving a resolution of 75 mK over a temperature range of -30 to 70 °C. The line sensitivity of the sensor is 2.8 °C/V.

A 6.4 nW 1.7% Relative Inaccuracy CMOS Temperature Sensor Utilizing Sub-Thermal Drain Voltage Stabilization and Frequency Locked Loop

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9129800

**Abstract:**

A CMOS Voltage Level Detector (VLD) circuit is proposed for IoT systems which operates near the minimum energy point. It can accurately detect VCC levels of 550-640mV, making it one of the lowest voltage VLDs reported to date. A novel pull-up circuit is utilized to accurately detect fast VCC ramps of 10’s of micro seconds, which are faster than the power-up of the VLD itself. This feature enables it to operate at a low power consumption of 2.6uW. A low voltage, charge-pumped bandgap reference is utilized with a highly accurate comparator to achieve a 35mV variation across temperature and a random variation sigma of 1.68mV. This circuit is one of the lowest voltage, most highly accurate and fastest ramp-detect VLDs that have been reported in the literature.

An Accurate 0.55V 2.6 µW Voltage Level Detector

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9141323

**Abstract:**

This letter presents a low-power dynamic comparator for ultralow power applications. The prototype is designed in a 65-nm CMOS process with a supply voltage of 1 V and is compared against the widely used double tail latch comparator in terms of power consumption and input referred rms noise. The addition of cross-coupled devices to the input differential pair prevents the comparator internal nodes from fully discharging to ground in contrast to the conventional architecture. This reduces the power consumption while achieving similar noise levels. Measurements demonstrate that the proposed comparator achieves an input referred rms noise voltage of 220 µV against 210 µV for the conventional comparator with a 30% reduction in power. The proposed circuit consumes 0.19-pJ energy per comparison.

A Low-Power 1-V Supply Dynamic Comparator

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9154469

**Abstract:**

An electrochemical sensor signal acquisition chain consisting of a multichannel bidirectional current-mirror-based potentiostat and a multiplexed current-input delta–sigma ADC is presented. To enable the integration of the circuit into wirelessly powered point-of-care (PoC) diagnostics, a low-voltage and low-power implementation of the circuit is proposed. This is achieved by the use of a class-AB-amplifier based sensor front-end, which keeps the power and voltage headroom consumption at a minimum. Output stage current replication in the front-end amplifier enables bidirectional current sensing without additional measures. The proposed circuit achieves a wide dynamic range and the highest power efficiency among similar systems.

A Bidirectional Current-Mirror-Based Potentiostat Using a Slice-Based Class-AB Amplifier

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9129816

**Abstract:**

Active rectifier, biomedical implantable devices, coarsefine, delay compensation, wireless power transfer (WPT). This letter presents an active rectiﬁer with SAR-assisted coarse-ﬁne adaptive digital delay compensation technique for biomedical implantable devices. Both on- and off-delays are compensated by adjusting the comparator offset. In order to achieve accurate zero-voltage switching against process, voltage, and temperature variations, a two-step coarse-ﬁne digital tuning method is introduced. The coarse-tuning phase and the ﬁne-tuning phase are controlled by a 7-bit SAR controller and a 3-bit bidirectional counter, respectively. The proposed technique could avoid reverse current and achieve maximum conduction time for power switches. Meanwhile, it is suitable for compensating power switch with large on/off-delay variation.

A 13.56-MHz Active Rectifier with SAR-Assisted Coarse-Fine Adaptive Digital Delay Compensation for Biomedical Implantable Devices

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9152041

**Abstract:**

A multichannel impedance-sensing CMOS chip for the readout of non-invasive light detectors in Silicon Photonics is presented. The performance of the lock-in phase-sensitive demodulator is improved thanks to a capacitive feedback transimpedance amplifier (TIA) equipped with an active discharge network, able to keep a DC output offset lower than 3 mV for leakage currents up to 4 nA while injecting a noise lower than 40 fA/sqrt(Hz). The addition of a sensor capacitance compensation system at the input of the chip allows a 30-fold increase of the stimulation amplitude, enabling the tracking of sub-picoSiemens conductance variations on a baseline of few uS, with a bandwidth of 70 Hz. The chip performance opens the way to multipoint monitoring of complex photonic systems, addressing the challenges posed by the growing complexity of these architectures.

Wide Dynamic Range Multichannel Lock-in Amplifier for Contactless Optical Sensors with Sub-Ps Resolution

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9023.pdf

**Abstract:**

This paper focuses on the comparison of various advanced substrates such as trap-rich (TR), porous silicon (PSi), gold-doped (Au-Si) and smart-implants PN-junction (DP) in terms of RF performances. Both small- and large-signal measurements were performed, including the study of the influence of temperature and bias voltage. The purpose of this paper is to provide an overview of the characteristics of these multiple substrates to facilitate design choices for RF-IC applications.

High-Temperature Characterization of Novel Silicon-Based Substrate Solutions for RF-IC Applications

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9292.pdf

**Abstract:**

This paper presents dual-layer proton irradiation profile to improve the thermal stability of high-resistivity substrate formed by low-fluence proton irradiation. Dual-layer irradiation uses targeted irradiation to the Si-SiO2 interface to reduce the fluence required for preventing the formation of conduction layer after annealing. Thermal stability of effective substrate resistivity is evaluated indirectly through inductor Q-factor measurement before and after annealing at 260°C for 1 minute. With the same total fluence, measurement result shows the proposed dual-layer irradiation profile can suppress post-anneal Q-factor degradation from 17% to 1%. The required active devices margin from irradiated area is also reduced by 26%.

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