United States

Doping with La is a promising route to improve endurance of ferroelectric Hf0.5Zr0.5O2 film for non-volatile random access memories [1-2]. However, the beneficial effect of La on the endurance of polycrystalline films may be accompanied by degradation of the retention [3]. Here, we have investigated whether this endurance - retention dilemma also occurs in La-doped epitaxial Hf0.5Zr0.5O2 films.
Epitaxial 1% La-doped Hf0.5Zr0.5O2 films of thickness in the 4.5 - 13 nm range were deposited by pulsed laser deposition on SrTiO3(001) (STO) and STO/Si(001) substrates, buffered with a La2/3Sr1/3MnO3 electrode. The films structure was studied by X-ray diffraction (XRD) and surface topography was studied using atomic force microscopy. Top Pt electrodes were deposited on top of the films to characterize their ferroelectric properties (polarization, leakage, endurance and retention).
Compared to undoped epitaxial Hf0.5Zr0.5O2 films [4-5], large values of polarization are obtained in a wider thickness range, whereas the coercive fields are similar, and the leakage current is substantially reduced. Compared to polycrystalline La-doped films [2-3], wake-up effect of epitaxial La-doped films is limited to a few cycles. Despite fatigue, endurance in epitaxial La-doped films is more than 1010 cycles, and this good property is accompanied by excellent retention of more than 10 years at room temperature. These results demonstrate that the wake-up effect and endurance–retention dilemma are not intrinsic in La-doped Hf0.5Zr0.5O2.

Materials Challenges for Memory

Epitaxial La-Doped Hf0.5Zr0.5O2 Thin Films with Enhanced Ferroelectric Properties

epitaxial oxides on silicon

epitaxial hfo2

hf0.5zr0.5o2

ferroelectric oxides

ferroelectric hfo2

#### Welcome to the 62nd IEEE International Reliability Physics Symposium (IRPS)! 
**The 2024 IEEE International Reliability Physics Symposium (IRPS) was held in Dallas, Texas from April 14 to 18, 2024.** 

[![](https://assets.underline.io/uploads/markdown_image/1/image/9cc005f94b4ba4a81918eb49e0a51057.png)](https://underline.io/events/446/reception)
[![](https://assets.underline.io/uploads/markdown_image/1/image/acae953ba70ae2a57eed7b0250d6dd7d.png)](https://www.irps.org/)
[![](https://assets.underline.io/uploads/markdown_image/1/image/e1806748f2fc69f825e596872a7afdfd.png)](https://drive.google.com/drive/folders/1SmhpLZD9swYxrfP0TYF6327QTIciy3tV?usp=drive_link)
 

**[IRPS 2024 eGuide](https://drive.google.com/file/d/1DHxkWbafodK_D2HlDi7lwRK7KatgBgBD/view?usp=drive_link)** 
Please save the zip file locally and click the "start.pdf" to view the file. 
 
**IRPS 2024 General Chair Welcome Message**

On behalf of the Management Committee of the IEEE International Reliability Physics Symposium (IRPS) and the IRPS Board of Directors, it gives me great pleasure to extend a warm welcome to all who are planning to attend the IRPS 2024, scheduled to take place from April 14-18, 2024, in Dallas, TX. 
Over its 62-year history, IRPS has solidified its position as the premiere conference for engineers and scientists to present new and original work in the field of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and other parts of the world, IRPS aims to deepen our understanding of reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS offers diverse opportunities for attendees to enhance their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The IRPS 2024 technical activities will begin with two days of a total of twenty tutorial sessions covering a broad spectrum of emerging reliability topics beyond CMOS device, circuit and system reliability. These sessions are devoted to both newcomers as well as experts. Three reliability Year in Review (YIR) talks focusing on neuromorphic computing, dielectric breakdown in leading edge devices, and GaN technology will be provided on Monday after the tutorials.

The IRPS 2024 technical program will feature four distinguished keynote talks in the plenary sessions delivered by Prof. Shinichi Takagi from The University of Tokyo and Dr. Su Jin Ahn from Samsung on Tuesday, Dr. Rajeev Malik from IBM on Wednesday, and Dr. Sameer Pendharkar from Texas Instruments on Thursday. The technical program, organized into three parallel tracks, consists of contributed and seventeen invited papers from leaders in industry and academia. Additionally, two invited talks by recipients of paper awards from our sister conferences, European Symposium on Reliability of Electron Device Failure Physics and Analysis (ESREF) 2023 and the International Integrated Reliability Workshop (IIRW) 2023, will be given in the technical program. 

Tuesday evening will host ten workshops, offering an opportunity for in-depth, face-to-face discussions on emerging reliability challenges, including the three IRPS 2024 focus topics. A poster session will be held in the Austin Ranch outside the symposium building on Wednesday evening. Both events are sure to be lively. The IRPS 2024 and the International ESD Workshop (IEW) will be co-hosted with IEW registrants participating in both IRPS and IEW programs.

The IRPS 2024 will adopt a hybrid conference style, allowing virtual access to live oral presentations hosted by the Underline. Real-time streaming of all technical events (excluding Workshops and Posters) will be available in the US Central Timezone, providing virtual attendees with Q&A opportunities. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees after the symposium. All authors will be presenting in person.

Finally, I would like to extend my extreme gratitude to our patrons, exhibitors, and all participants for their invaluable support, which makes IRPS successful. 

Please enjoy the IRPS 2024!

Koji Eriguchi, General Chair 
of 2024 IRPS Management Committee
 
**About IRPS** 
The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

You need to log in with the email address you registered with. Access credentials have been sent to your email. 

Please be sure to check your spam and other email folders if you do not see an email confirmation right away.

Please log in to explore this event.

It looks like you are not registered for this event. 

To access the site please register [**here**](https://www.irps.org/registration-fees). 

Please register!

IRPS 2024 Main Conference

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. 

poster


![](https://assets.underline.io/uploads/markdown_image/1/image/2e10c515564e9ec3287ee4c664011c20.png)

The energy cost of storing and moving data is enormous, and is growing at such a rapid pace that within a few years the power demand may overwhelm some developed nations. Non-volatile memory (NVM) and neuromorphic computing are enabling critical advances in this area, but there are many scientific and technological challenges. This conference will cover the materials challenges of different memory technologies, from the fundamental processes and mechanisms, to industry perspectives on materials specifications and manufacturing.

As the promising candidate of artificial synapses, memristor has attracted more and more interest in the future neuromorphic networks. Compared to the traditional Si-based devices, the flexible memristors exhibit light-weight, wearable, and cheap advantages. Inorganic compounds have excellent electrical performance but suffer from weak flex characteristics, and it can’t bear large bent degrees. The organic-inorganic hybrid materials combine flexible properties with outstanding electrical performance, so it is a favorable choice for the flexible memristor materials. Here, some essential synaptic functions are demonstrated in the Al-based hydroquinone (HQ) organic-inorganic hybrid film memristor on ITO-coated flexible PET substrate. Setting different set compliance currents and reset voltages, multi-level resistances are achieved at a steady state with little fluctuation. Through the pulse stimulation, paired-pulse facilitation, short-term to long-term plasticity transition and spike-timing-dependent plasticity (STDP) are successfully emulated. After 10000 times bent test (curvature radius ~4.5 mm), the electrical performance also exhibits stable RHRS/RLRS ratio ~1000, and essential synaptic functions emulation without serious failure resistive switching. The flexible memristor is potential to apply in the wearable electronics and smart artificial skins.


High-performance Flexible Memristor Based on Organic-Inorganic Hybrid Thin Film Derived from Molecular Layer Deposition for Artificial Synapse Device

The discovery of memristor, theorized in 1971 by L. Chua, has led to the development of novel artificial neuromorphic concepts and devices, including ferroelectric-based ones. Ferroelectric Tunnel Junction (FTJ) type memristors based on zirconium-doped hafnium oxide, Hf_0.5 Zr_0.5 O_2 (HZO) have recently displayed synaptic learning capabilities. In addition, HZO processes are already fully compatible with silicon CMOS industry with oxide layers thinner than 10 nm. In the present work, the HZO layer is realized by room temperature magnetron sputtering of a Hf_0.5 Zr_0.5 O_2 ceramic target and subsequently crystallized by rapid thermal annealing. Using different bottom electrode layers (germanium, titanium nitride, platinum) grown on silicon and different substrates (n-doped silicon, n-doped germanium), we studied the effect on the stabilized crystalline phase and microstructure (Fig), band structure alignment and electrical properties of thin HZO films. Furthermore, we explored the effect of ultra-thin buffer layers between the electrodes and the HZO layer, trading on the material, the position and the thickness. We exploited X-ray photoemission spectroscopy to analyze the chemistry and the electronic state of the electrodes/HZO interface. X-ray reflectometry and grazing incidence X-ray diffraction (GIXRD) were used to probe the thickness and structural characteristics of the HZO layer, whose ferroelectricity is associated to the polar orthorhombic phase. We will discuss our results in the framework of structural, chemical and physical properties of the different electrode/ferroelectric interfaces and their effect on the electrical properties of thin HZO-based junctions.

Influence of bottom electrodes on HZO thin film features

Resistive switching (RS) memories have been a crucial component for the requirements of the Internet of Things (IoT) which demands ultra-low power and high-density devices with new computing principles, exploiting low cost green products and technologies. Most of the reported resistive switching devices use conventional methods (PVD and CVD) which are quite expensive due to their up-scale production. Solution-processing methods have been improved, being now a reliable technology that offers many advantages for RS devices such as, high versatility, large area uniformity, transparency, low-cost and a simple fabrication of two-terminal structures. Solution-based metal oxide RS devices are emergent and promising non-volatile memories for future electronics. 
In this work, we review the present status of solution-based metal oxide RS devices is highlighted as well as discuss the solution synthesis parameters which induce a massive influence on the overall performance of these devices.[1] Next, a precise analysis of the most reported transition metal oxide thin films and electrode interface is presented. Then the recent advances on RS devices that will allow the massive production and compatibility with flexible substrates targeting low cost for neuromorphic and memory applications are discussed. Finally, the main challenges in solution-based metal oxide RS devices are discussed and future trends are proposed.

Recent Challenges and the Future of Metal Oxide Resistive Switching Devices

Memristors have been at the forefront of nanoelectronics research for the last decade, offering a valuable component to reconfigurable computing. 
Over this time period a number of publications have studied most of their aspects, generally centering around their static state-dependent programmability. 
In the present work, the behavior of metal-oxide memristors under a noninvasive
AC perturbation in a range of frequencies is studied. Metal-oxide memristors present a variable cut-off frequency when their state is switched. 
Also, they are found to behave as RC low-pass filters and thus can be used as reconfigurable filters. 
The usable reconfigurability window of the devices can be tailored to encompass specific frequency ranges by amending the devices’ capacitance, through engineering of its geometrical characteristics, such as area and thickness. Furthermore, by changing the active material of the device the behavior remains consistent, pointing to a unified behavior across metal-oxide memristors, irrespective of material used. This study provides useful insights for the eventual usage of devices in AC circuits and extends current knowledge by characterising their frequency dependent characteristics.

Frequency Response of Metal-Oxide Memristors

Electronic devices that can simulate the dynamics of neurotransmission in the human body are of great interest for the development of artificial intelligence in modern information technology. In this paper, an artificial nociceptor realized by a single metal-oxide nanobelt device with a unique capacitive-coupled threshold switching behavior is demonstrated. Via thermal admittance spectroscopy and temperature dependent sweeping study, the properties of the nanobelt devices are determined by Schottky emission at low bias and by defect assisted quantum tunneling at high bias subject to a threshold voltage. The low activation energy associated with dynamic electron trapping gives rise to a voltage-dependent volatile threshold switching behavior. This threshold switching behavior allows the emulation of several characteristic features of a nociceptor, a critical type of sensory neuron in the human body, including “threshold”, “relaxation”, “no adaptation”, “allodynia” and “hyperalgesia” behaviors, essential for the realization of electronic sensory receptors that detect noxious stimuli and signal rapid warning to the central nervous system. One-dimensional metal oxide nanobelt devices of this type yield multifunctional nociceptor performance that is fundamental for applications in artificial intelligence systems, representing a key step in the realization of neural integrated devices via a bottom-up approach.

Threshold Switching in Single Metal‐Oxide Nanobelt Devices Emulating an Artificial Nociceptor

One of the most desirable attributes of non-volatile memories and memristors is a fast and non-destructive readout of their resistive state. Prototypical ferroelectric memories use the bulk photovoltaic response associated to the polarization of ferroelectric films to address this requirement by optically sensing binary memory cells. A more advanced type of non-volatile memories are ferroelectric tunnel junctions. They feature resistive state ratios RHigh/RLow of 10^6, with an accessible continuum of resistive states, making them promising candidates for neuromorphic computing applications. However, tunnel junctions have ultrathin ferroelectric barriers in the range 3-6 nm that prevented a measurable photovoltaic response originated in the bulk of the barrier. We present the optical sensing of the resistive state of a ferroelectric tunnel junction using the Schottky barrier formed in the bottom interface to dramatically enhance its optical response. Our FTJ based on the La0.7Sr0.3MnO3/BaTiO3 (LSMO/BTO) interface, one of the best performing and studied material combinations, builds up an optically active Schottky barrier whose properties can be tuned by performing a resistive switch. By integrating a transparent conducting top electrode of ITO, we make the junctions optically accessible to light. UV illumination with 3.3 eV energy, exceeding the BTO bandgap, generates a solid photovoltaic response in the high resistance state originated in the Schottky barrier, with an open circuit voltage Voc of 0.4 V at 20 K. The photovoltaic effect is absent using lower energy red light (1.9 eV). In the RLow state, the Schottky barrier is removed and the photo response disappears, enabling the optical sensing of the resistive state.


Optically Active Schottky Barrier in La0.7Sr0.3MnO3/BaTiO3/ITO Ferroelectric Tunnel Junction Memories

Development of complementary metal–oxide–semiconductor (CMOS) logic is expected to approach its fundamental limit as the scaling down of the CMOS technology is reaching an end. As a route to extend the technology roadmap beyond traditional CMOS logic, novel spin-based logic architectures are being developed to provide nonvolatile data retention, near-zero leakage, and scalability. In particular, architectures based on magnetic domain walls (DWs) take the advantage of the fast motion, high density, non-volatility and flexible design of DWs to process and store information. Such schemes have so far relied on DW manipulation and clocking using an external magnetic field, which hinders their implementation in dense, large-scale chips. Here we demonstrate a method for performing all-electric logic operations and cascading using DW racetracks. Our concept for the magnetic DW logic is based on efficient DW motion induced by spin-orbit torques (SOTs) and recently developed chiral coupling between adjacent magnets where the magnetic anisotropy competes with the interfacial Dzyaloshinskii–Moriya interaction (DMI). Our work provides a viable platform for scalable all-electric magnetic logic, paving the way for memory-in-logic applications.

Current-driven magnetic domain-wall logic

Non-volatile memories include magnetic random access memories (MRAM), reverse transfer magnetoresistive random access memory (STT-MRAM), phase change random access memory (PCRAM), and resistive random access memory (RRAM), the latter being non- volatiles emerging. The RRAMs memories are characterized for having a metal/insulator/metal architecture; however, we proposed an alternative configuration based on metal/oxide-diluted magnetic semiconductors (O-DMS)/metal due to the promising magnetic control performance of resistive switching. This work presents a study of the structural, morphological, magnetic, and electric properties of Cobalt doped ZnO and TiO2 thin films fabricated via DC magnetron sputtering. HR-SEM and AFM micrographs evidencing the formation of small grains in the surface associated with the growth mechanism for the thin films. Electrical and magnetic characterization shows a contribution of lattice-free electrons, produced for oxygen vacancies, and Co ions randomly located into oxide semiconductor matrix, in the SET and RESET states. Comparative study of ZnO and TiO2 semiconductor matrices suggestion the low energy consumption in the process and the expansion of storage capacity, due to both high and low resistive states modified for the magnetic field applied.

Cobalt doping effect on ZnO and TiO2 Based on Resistive Switching Memory Device

In this work, we present structural, morphological, magnetic, and electrical properties of GaSb/Mn multilayer deposited via DC magnetron sputtering at room temperature and 423 K. Through Raman measurements, it was possible to determine the formation of p-type GaSb layers. HR-SEM shows the multilayer architecture with columnar microstructure in the formation of layers with grain nucleation in the surface. The effect of the substrate temperature contributed to the stress effects on the layers. Formation of the interlayers between GaSb and Mn layer was determined via Rutherford Back-Scattering spectra. These interlayers were associated with diffusion process during deposition and contributed to the magnetic behavior of multilayers. A ferromagnetic-like behavior was observed in the multilayers associated to the domains formation due to the interlayers presence. I-V curves show a RESET-SET states of multilayer system with bipolar behavior, which can be modified from external magnetic fields.


GaSb/Mn Multilayers Via DC Magnetron Sputtering: A Study of Interface Structure for Non-Volatile Memories Applications

Resistive switching memories are a serious contender for high density computing memory in the future. The operation of valence change memories specifically relies on a migration of defects within the oxide layer. This is assumed to be the case in our silicon dioxide devices[1]. It is therefore crucial we understand the properties of the migrating defects, such as their mobilities, so that we can simulate devices more effectively and with better precision. We are investigating a phenomenon observed within oxide capacitors known as the current transient[2] as one potential mechanism to probe defect mobilities and their effect on interface barriers. 
The current transient phenomenon arises when a constant voltage is applied to a leaky oxide capacitor causing a distinctive transient to be observed. The device current initially increases rapidly up to a maximum, then levels out, and finally decays slowley. This results in a characteristic peak observed in the current-time plot. Although we have previously used it to carry out computations[3], it has also been suggested that oxygen vacancy mobilities can be obtained from such transients[4] by analysing the dynamics using a space charge limited current (SCLC) model[2,5]. However, our investigations into this effect suggest that the SCLC theory may not be an accurate representation of the changes occurring within our own devices. 
To investigate the validity of the SCLC model we have developed techniques to repeatably induce current transients within devices as well as novel analytical techniques that reveal more information on the dynamics of the transient. In doing so, we have been able to develop an alternative model that may help explain the current transient as a two-part process which is the result of charge injection and a field drive migration of defects occurring in parallel.
While this model differs to the SCLC theory, it still predicts defect mobility to be a measurable observable and may provide a more accurate representation of this quantity. Additionally, it may allow us to determine interface barrier heights at the source of electron injection - something which cannot be determined from the SCLC analysis. 
Our new approach to analysing current transients may prove to be an important probe into the dynamics of defects within resistive switching memories.

1 A. Mehonic, M.S. Munde, W.H. Ng, M. Buckwell, L. Montesi, M. Bosman, A.L. Shluger, and A.J. Kenyon, Microelectronic Engineering 178, 98 (2017).
2 A. Many and G. Rakavy, Physical Review 126, 1980 (1962).
3 D.J. Mannion, A. Mehonic, W.H. Ng, and A.J. Kenyon, Frontiers in Neuroscience 13, 1386 (2020).
4 S. Zafar, R.E. Jones, B. Jiang, B. White, P. Chu, D. Taylor, and S. Gillespie, Applied Physics Letters 73, 175 (1998).
5 M.A. Lampert and P. Mark, (1970).




Premium content

Downloads

Next from Materials Challenges for Memory

High-performance Flexible Memristor Based on Organic-Inorganic Hybrid Thin Film Derived from Molecular Layer Deposition for Artificial Synapse Device

Similar lecture

Investigation of Read Disturb for Hf0.5Zr0.5O2 Ferroelectric Field-Effect Transistors Based Neuromorphic Applications