France

The IPCEI program at GF includes innovation along all technology readiness levels (TRLs). One example for very low TRL is the Reconficurable FET based on Schottky Barriers, close to 22FDX-processing. It enables camouflaging circuits for security applications, by e.g. providing NAND or NOR type cells, that can not be identified by reverse engineering. Another example is the development of a mmWave-variant of 22FDX allowing for operation frequencies typically in the 28-80 GHz regime, but also ranging up to 140 GHz. Characterisation of devices up to 3-4 times the operational frequency, a prerequisite for operation of the devices at these frequencies and showcases in the GHz regime for auto-Radar, 5 G and imaging radar are shown. These are just two examples, how the energy efficient 22FDX-technology at GF is enrichened by specialized variants and applications-specific- features.

ESSCIRC ESSDERC Educational Events

Novel devices for security and showcases for mmwave with 22FDXTM

mmwave

fdsoi

cmos

security

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

ESSCIRC ESSDERC 2021

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





technical paper

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

Please register for educational events at the following link: https://www.registerme.eu/event/esscirc-essderc-2021/

Please register for the ESSCIRC/ESSDERC Educational Events to join the event.

The Educational Events of ESSCIRC ESSDERC 2021. 

Mixed signal circuits are at the core of the IoT where the main sales
argument for devices is their capability to interact with the environment through
multiple sensors and actuators. Unfortunately, mixed signal integrated circuits,
unlike digital circuits, do not scale according to Moore’s law. The 3D-MUSE
project investigates emerging monolithic/sequential integration technology that
integrates CMOS tiers of different technology nodes to tackle this scaling challenge.
This technology offers 3D inter-tier connection densities on par with
horizontal in-tier CMOS interconnection densities, thus allowing transistor level
placement of circuit components across tiers at minimal to no area overhead cost.
Mixed signal functional circuit blocks can thus be implemented in a volume and
combine device options from different CMOS technology nodes to maximum advantage, e.g. reducing parasitics, area, cost and power, and gaining processing
speed. The 3D-MUSE project combines efforts from 3D technology developers
and ASIC design groups to showcase examples of such mixed-signal systems,
enabling smart sensor interfaces implemented as ’systems-in-cube’.

Introduction: The 3D-MUSE project

The aim of this paper is to present the 3D-sequential integration and its main prospective application sectors. The presentation will also give a synoptic view of all the key enabling process steps required to build high performance Si CMOS integrated by 3D-sequential with thermal budget preserving the integrity of active devices and interconnects and will sketch a status and prospect on current low temperature device performanc

3D sequential integration: opportunities and challenges

Design of 3D ICs is mainly done in separated design environments for each tier, assuming that communication channels between tiers are user-defined and fixed at the beginning of the design process1,2. Suitable for 3D stacking based on TSV or Hybrid Bonding technologies because of the low granularity of these 3D interconnect elements, this methodology becomes more difficult to apply to 3D sequential technologies once trying to integrate Monolithic Inter-tier Vias (MIV) with higher density (around 1.108 vias per mm2). In this paper, we describe a methodology to create a unified design environment, which includes several technologies attached to different tiers. Main advantage of this methodology is that designing a 3D circuit may no more require several design environments, thus simplifying simulations, verifications and layout finishing.

Merging PDKs to build a multi-process multi-tier 3D design environment

A 14-bits cyclic ADC is implemented in two-tier 3D sequential integration
(3DSI) multi-process technology. The ADC specifications are intended
for the daughter-payloads of the investigation of cusp irregularities (ICI) sounding
rocket series, i.e. small sensor platforms that are ejected in-flight to measure
plasma electron density in a cloud around the rocket. The two 3DSI processes
used are a 65nm SOI technology with 28nm shrink transistors in the top tier
and 28nm FDSOI as the bottom tier. This work aims to explore architectures
in a high-density interconnect 3D sequential integration process for area and
power reduction, exploiting fine-grained transistor placement as well as device
parameter optimization having the choice of two different CMOS technologies
for each individual device.

14-bits Cyclic ADC in 3D sequential multi-process Technology

This presentations deals with innovative approaches of 3D stacking Image sensors. Comparisons with conventionnal 3D vs sequential stacking is described.

Innovative Fine Pitch Architectures dedicated to Image Sensors: from Hybrid Bonding to 3D Sequential integration

The presentation is related to the EU-funded 3D-MUSE project where an extra layer of transistors is produced on top of a standard CMOS technology. Some readout circuits for radiation will be presented as well as how they can make use of several transistor layers. Examples are a multi-channel PMT, a thermal image sensor and a light radar. A simple TDC (Time to Digital Converter) will also be presented.

3D Integrated Circuits for Radiation Sensor Readout

In an industry wide consensus perpendicular spin-transfer-torque magnetic random-access memory (pSTT-MRAM) has matured to the memory of choice for replacing embedded FLASH solutions in the 2X nm technology nodes and beyond. However, especially this first entry point as a replacement for solder-reflow-capable eFLASH implies stringent requirements when it comes to high temperature data storage capabilities. In highly scaled pSTT-MRAM this demanding non-volatility can only be achieved by advanced free layer engineering. This energy barrier modulation needs to be carefully balanced in the boundary conditions of power consumption and endurance requirements. Sustaining and predicting this balance already at film-level or during patterning will be highly rewarding for the reliable manufacturing of this new technology. Here we present an early view on film-level and post-patterning magnetic metrology for embedded pSTT-MRAM.

Magnetic Metrology on Fully Integrated Embedded STT-MRAM

The architectural innovations of a new FPGA is presented.
The programmable Element, the routing structure and innovative switchboxes are explaned.

Novel Architecture for European FPGA

The modern world witnesses an ever-growing variety of consumer, home, automotive and industrial devices with network connectivity. 
Security is a crucial aspect in such systems and stakeholders will confirm that security constantly evolving. 
Therefore, NXP is very much involved in developing resilient, secure and trustworthy products that are a crucial building block for European data sovereignty. 
This results in the foundation that our customers use to build secure products.

In this presentation we will highlight the contributions of NXP Semiconductors Austria in the scope of IPCEI. 
This ranges from implementation security for high security products like Roots of Trust, 
over safe and secure battery management system for the green revolution as well as innovative 
application of technology for security use cases like Ultra-Wide-Band (UWB) radio for car access.

A connected world – Why security matters

5G standards effective deployment drives considerable technology challenges and implications on mobile devices design and requires innovative solutions to solve them. 
At the RF Front End Modules (FEM) level, the usage of new frequency bands, the complex use of the frequency bands (Carrier Aggregation, MIMO, QAM) and the coexistence with 4G networks are challenging the limits of existing acoustic filter technologies. 
A promising approach combining a thin single crystal LiTaO3 layer bonded on a Silicon substrate - so called Piezo On Insulator (POI) – together with the existing Surface Acoustic Wave (SAW) filter technology, enables to take advantage of guided waves that do not suffer from any radiation leakage. This SAW on POI approach will extend the use of the existing SAW technologies for higher performance integrated acoustic devices.
Triggered by the 5G filter market demand, the Smart CutTM technology has enabled high performance POI substrates supply chain in volume manufacturing, and paves the way to new design approaches for many applications beyond the Smartphone market.


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