France

In an industry wide consensus perpendicular spin-transfer-torque magnetic random-access memory (pSTT-MRAM) has matured to the memory of choice for replacing embedded FLASH solutions in the 2X nm technology nodes and beyond. However, especially this first entry point as a replacement for solder-reflow-capable eFLASH implies stringent requirements when it comes to high temperature data storage capabilities. In highly scaled pSTT-MRAM this demanding non-volatility can only be achieved by advanced free layer engineering. This energy barrier modulation needs to be carefully balanced in the boundary conditions of power consumption and endurance requirements. Sustaining and predicting this balance already at film-level or during patterning will be highly rewarding for the reliable manufacturing of this new technology. Here we present an early view on film-level and post-patterning magnetic metrology for embedded pSTT-MRAM.

ESSCIRC ESSDERC Educational Events

Magnetic Metrology on Fully Integrated Embedded STT-MRAM

mram

metrology

The 15th Joint MMM-INTERMAG Conference (2022 Joint) is sponsored jointly by AIP Publishing and the IEEE Magnetics Society. Members of the international scientific and engineering communities interested in recent developments in fundamental and applied magnetism are invited to attend and contribute to the technical sessions. The technical program will include invited and contributed papers in oral and poster sessions, invited symposia, a plenary session, and an evening session, with about 1500 presentations overall. This Conference provides an outstanding opportunity for worldwide participants to meet their colleagues and collaborators and discuss developments in all areas of magnetism research.

The 2022 Joint Conference will offer both in-person and prerecorded on-demand content.

For tickets to the event, please register at the following link: https://magnetism.org/register

Please register for the Joint MMM-Intermag conference to join the event.

2022 Joint MMM-INTERMAG

This Conference provides an outstanding opportunity for worldwide participants to meet their colleagues and collaborators and discuss developments in all areas of magnetism research.

technical paper

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021<br>
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021<br>
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

Please register for educational events at the following link: https://www.registerme.eu/event/esscirc-essderc-2021/

Please register for the ESSCIRC/ESSDERC Educational Events to join the event.

The Educational Events of ESSCIRC ESSDERC 2021. 

Europe is facing one of the biggest challenges of its history: that of preserving a viable environment for the decades to come. On human consciousness of its environmental impact, Prof Bartlet says “The greatest shortcoming of the human race is our inability to understand the exponential function” [1]. ICT was, and still is, driven by exponential functions (Moore’s law, Ops/ Watt, data exchanges volume worldwide, ...). But each exponential has its sustainability limits which are often reached sooner than expected. In ICT history to date, when those limits are reached, they are overcome by a technology breakthrough. By way of example, there was the CMOS (Complementary Metal-Oxide- Semiconductor) technology, a product of laboratory curiosity of the 1980s when bipolar transistor power consumption was too high. New integrated system (multi-core processor) and device (SOI, FinFET,...) architectures entered the market when energy consumption limits were reached by CPUs; CMOS is still today the much cheaper and reliably power efficient technology for the development and growth of the Internet of Things. Awareness of the rapid proliferation of wirelessly connected objects around us gives rise to questions and fears among the public. There is a need for more transparency on the environmental footprint of ICT and a need to establish an ambitious roadmap, at research and industrial levels, for moving into a virtuous cycle of eco- innovation.

In this presentation, we propose pathways to maintain or even reduce global (exponential) use of energy and materials for ICT.

HiPEAC Vision 2021: key recommendations and the importance of sustainability

Electronics is increasingly introduced in our society and the Internet-of-Things (IoT) contribute extensively to this trend. Indeed, their number is expected to boom in the next years (+10-30% per year). Although this could enable positive effects both on our society and our environment through optimization and monitoring, the massive deployment of IoT will come together with an undeniable environmental burden which is often overlooked. As it has been shown that the main environmental impacts of electronics do not reside necessary in the use phase but rather in the raw-material extraction and production phases (which is especially true for battery-powered devices), life cycle approaches are needed to better understand the impacts of the IoT in order to avoid worsening the current environmental situation.
In this talk, we first present a macroscopic analysis focusing mainly on the energy and carbon footprint of ICT sub-sectors. It shows that the following of exponential trends such as Moore’s law will very unlikely lead to an absolute decrease of GHG emissions if sobriety is not considered together with efficiency improvements. Then, we propose a framework based on hardware profiles to explore the environmental impacts of the production of IoT edge devices and discuss the coherence of the expected massive IoT deployment with respect to the Paris Agreement objectives. We also present eco-design use cases for IoT devices that are being developed in our labs, focusing on the environmental impacts of microelectronics pressure sensors and water quality monitoring applications. In order to showcase how LCA can be used to support the development of new eco-design guidelines in the electronics sector, we study the interest of new design paradigms such as hybrid electronics. Finally, we call engineers to integrate systemic considerations when developing technologies, and we offer some concrete perspectives and tools that can be applied by engineers to support the dissemination of more sustainable and appropriate electronics.

Towards a Green and Sustainable Digital Infrastructure: challenges and opportunities

This presentation motivates neuromorphic computing and memristive devices as a power efficient alternative for applications in artificial intelligence. It also covers recent device-level results of threshold and bipolar memristive switching in two-dimensional materials. finally, it provides an overview of the large scale Clusters4Future initiative "NeuroSys" in Germany, that is expected to launch in the Aachen region in Germany in January 2022.

Neuromorphic Computing Devices based on Two-Dimensional Materials

The climate crisis calls for urgent actions towards sustainability as an integral component of businesses and regulations. With its large and growing environmental footprint, the Information and Communication Technology sector is arguably a large part of the problem, but also a part of the solution. Fabrication of integrated circuits is an energy and resource intensive process and the drive towards higher performance and increased functionality increases the process complexity dramatically from node to node. Traditionally, the improvement between technology nodes is evaluated using Power, Performance, Area and Cost (PPAC) metrics in a Design Technology Co-Optimization (DTCO) completely neglecting sustainability. However, this established framework provides an opportunity to do early sustainability assessments of future technologies all the way from material sourcing and fabrication to end of life. To demonstrate this approach, we evaluate the environmental impact, more specifically the energy and ultra-pure water (UPW) consumption as well as the greenhouse gas (GHG) emissions from manufacturing logic technology from past to future nodes. Our analysis shows a significant increase in the use of electricity (x3.46) and UPW (x2.3), as well as GHG emissions (x2.5) per wafer from iN28 to iN3. Together with improvements in performance and reduction in standard cell area, the environmental metrics normalized per transistor still reduce but the improvement is found to saturate at the most advanced nodes.

The environmental footprint of logic CMOS technologies

Mixed signal circuits are at the core of the IoT where the main sales
argument for devices is their capability to interact with the environment through
multiple sensors and actuators. Unfortunately, mixed signal integrated circuits,
unlike digital circuits, do not scale according to Moore’s law. The 3D-MUSE
project investigates emerging monolithic/sequential integration technology that
integrates CMOS tiers of different technology nodes to tackle this scaling challenge.
This technology offers 3D inter-tier connection densities on par with
horizontal in-tier CMOS interconnection densities, thus allowing transistor level
placement of circuit components across tiers at minimal to no area overhead cost.
Mixed signal functional circuit blocks can thus be implemented in a volume and
combine device options from different CMOS technology nodes to maximum advantage, e.g. reducing parasitics, area, cost and power, and gaining processing
speed. The 3D-MUSE project combines efforts from 3D technology developers
and ASIC design groups to showcase examples of such mixed-signal systems,
enabling smart sensor interfaces implemented as ’systems-in-cube’.

Introduction: The 3D-MUSE project

The aim of this paper is to present the 3D-sequential integration and its main prospective application sectors. The presentation will also give a synoptic view of all the key enabling process steps required to build high performance Si CMOS integrated by 3D-sequential with thermal budget preserving the integrity of active devices and interconnects and will sketch a status and prospect on current low temperature device performanc

3D sequential integration: opportunities and challenges

Design of 3D ICs is mainly done in separated design environments for each tier, assuming that communication channels between tiers are user-defined and fixed at the beginning of the design process1,2. Suitable for 3D stacking based on TSV or Hybrid Bonding technologies because of the low granularity of these 3D interconnect elements, this methodology becomes more difficult to apply to 3D sequential technologies once trying to integrate Monolithic Inter-tier Vias (MIV) with higher density (around 1.108 vias per mm2). In this paper, we describe a methodology to create a unified design environment, which includes several technologies attached to different tiers. Main advantage of this methodology is that designing a 3D circuit may no more require several design environments, thus simplifying simulations, verifications and layout finishing.

Merging PDKs to build a multi-process multi-tier 3D design environment

A 14-bits cyclic ADC is implemented in two-tier 3D sequential integration
(3DSI) multi-process technology. The ADC specifications are intended
for the daughter-payloads of the investigation of cusp irregularities (ICI) sounding
rocket series, i.e. small sensor platforms that are ejected in-flight to measure
plasma electron density in a cloud around the rocket. The two 3DSI processes
used are a 65nm SOI technology with 28nm shrink transistors in the top tier
and 28nm FDSOI as the bottom tier. This work aims to explore architectures
in a high-density interconnect 3D sequential integration process for area and
power reduction, exploiting fine-grained transistor placement as well as device
parameter optimization having the choice of two different CMOS technologies
for each individual device.

14-bits Cyclic ADC in 3D sequential multi-process Technology

This presentations deals with innovative approaches of 3D stacking Image sensors. Comparisons with conventionnal 3D vs sequential stacking is described.

Innovative Fine Pitch Architectures dedicated to Image Sensors: from Hybrid Bonding to 3D Sequential integration

The presentation is related to the EU-funded 3D-MUSE project where an extra layer of transistors is produced on top of a standard CMOS technology. Some readout circuits for radiation will be presented as well as how they can make use of several transistor layers. Examples are a multi-channel PMT, a thermal image sensor and a light radar. A simple TDC (Time to Digital Converter) will also be presented.

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