Italy

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9038.pdf

**Abstract:**

Apart from the well-known nonlinearity-induced fixed spurs, a DDSM divider-based fractional-N frequency synthesizer can manifest spurs with time-varying frequency offsets from the carrier; these are called wandering spurs. This paper presents experimental results for a 4.9 GHz CP-PLL fractional-N PLL featuring a modified MASH-based divider controller that implements wandering spur suppression. The synthesizer achieves a 20 dB reduction in the spectral envelope of the short-term output phase noise spectrum when compared to the standard MASH DDSM divider controller.

ESSCIRC ESSDERC 2021

Experimental Verification of Wandering Spur Suppression Technique in a 4.9 GHz Fractional-N Frequency Synthesizer

mash ddsm

fractional-n frequency synthesis

spurious tones

We are pleased to announce the Thirty-Ninth AAAI Conference on Artificial Intelligence (AAAI-25), which will be held in Philadelphia, Pennsylvania at the Pennsylvania Convention Center from February 25 to March 4, 2025.

The purpose of the AAAI conference series is to promote research in Artificial Intelligence (AI) and foster scientific exchange between researchers, practitioners, scientists, students, and engineers across the entirety of AI and its affiliated disciplines. AAAI-25 will feature technical paper presentations, special tracks, invited speakers, workshops, tutorials, poster sessions, senior member presentations, competitions, and exhibit programs, and a range of other activities to be announced.

### [Invited Speakers](https://aaai.org/conference/aaai/aaai-25/aaai-25-invited-speakers/)

Register [here](https://aaai.org/conference/aaai/aaai-25/registration/)

AAAI 2025

The purpose of the AAAI conference series is to promote research in Artificial Intelligence (AI) and foster scientific exchange between researchers, practitioners, scientists, students, and engineers across the entirety of AI and its affiliated disciplines. AAAI-25 will feature technical paper presentations, special tracks, invited speakers, workshops, tutorials, poster sessions, senior member presentations, competitions, and exhibit programs, and a range of other activities to be announced.



technical paper

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





**Please read the paper on the following link:**

https://1worldcontent.com/ess/9019.pdf

**Abstract:**

This paper presents a rail-to-rail class-AB operation amplifier with a proposed high-slew Miller compensation technique and current limiter for the output stage. Owing to the proposed Miller compensation technique, the amplifier achieves a maximum slew-rate of 30 V/μs while consuming a low quiescent current of 18μA. Among the state-of-the-art devices, the proposed amplifier has the best FOML of 34.72 for average slew-rate and FOMS of 10.11 for unity gain frequency.

A 18 μA Rail-to-Rail Class-AB Operational Amplifier with a High-Slew Miller Compensation (HSMC) Technique with 240% Settling Time Reduction in 0.18 μm

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9123.pdf

**Abstract:**

We present a widely tunable transimpedance amplifier (TIA) with a dc servo loop and an optional bandwidth extension. All resistors are implemented as multi-element pseudo-resistors, which feature high linearity, robustness against process and temperature, and a very wide tuning range of more than five decades. The TIA features a noise floor of 0.6fA/sqrt(Hz) at its maximum transimpedance of 150GOhm and a bandwidth of 2.9MHz at its minimum transimpedance of 440kOhm. A subsequent inverting amplifier stage provides an optional pole-zero compensation to extend the TIA\'s overall bandwidth. An additional dc servo loop can be used to compensate large dc currents.

A 440-kOhm to 150-GOhm Tunable Transimpedance Amplifier Based on Multi-Element Pseudo-Resistors

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9112.pdf

**Abstract:**

An internally compensated, two stage operational amplifier has been presented, fabricated using a-IGZO TFT technology. The highlight of the design is a new active load circuit based on positive feedback to realize high incremental impedance. The OpAmp has been fabricated and measured to have 57 dB DC-gain, 311 kHz unity-gain frequency and 75 deg. phase margin at 2.43mW power. To our knowledge, this design reports the highest achieved performance of an operational amplifier made in a-IGZO technology.

An a-IGZO TFT Based Op-Amp with 57 dB DC-Gain, 311 kHz Unity-Gain Freq., 75 deg. Phase Margin and 2.43 mW Power on Flexible Substrate

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9311.pdf

**Abstract:**

An on-chip analog waveform sampling system was demonstrated in a 65nm process focusing on extreme temperature step response measurements. Amplifier output waveforms were measured under different temperatures ranging from -40 degrees Celsius to 300 degrees Celsius. For reliability testing, the amplifiers were stressed at a 1.6x supply voltage and a 350 degrees Celsius stress temperature for a total stress time of 100 hours.

Extreme Temperature Characterization of Amplifier Response Up to 300 Degrees Celsius Using Integrated Heaters and On-Chip Samplers

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9091.pdf

**Abstract:**

A 272-GHz CMOS receiver (RX) for IEEE 802.15.3d, capable of an analog BPSK/QPSK demodulation based on a Costas loop, is presented. A QPSK demodulation is realized with the non-linear operation of a phase detector at the BPSKdemodulation Costas loop. An 8-Gbaud BPSK and a 4-Gbaud QPSK demodulation at the carrier frequency of 272.16 GHz (channel 58 of IEEE 802.15.3d) are achieved.

A 272-GHz CMOS Analog BPSK/QPSK Demodulator for IEEE 802.15.3d

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9204.pdf

**Abstract:**

This work reports on a low-intermediate frequency (IF) receiver front-end for Internet-of-Things applications. An un-balanced gate-boosted common-gate low-noise amplifier is proposed with 50% lower power dissipation compared with the conventional balanced topology. Channel-selection is performed with 2 complex poles centered at 2 MHz IF. The first complex pole is embedded in the passive down-conversion mixer, enabling higher in-band voltage gain and improved frequency selectivity. Built in 28-nm CMOS, the proposed front-end occupies an active area of 0.175 mm2, it is supplied with 1 V and consumes only 400 µW, while showing a minimum NF of 6.8 dB and an out-of-band IIP3 of -0.35 dBm. The performance meets Bluetooth Low-Energy requirements and is competitive with other sub-mW receivers.

A 400-µW Low-IF IoT Receiver Front-End with Tunable Charge-Sharing Complex Filter

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9228.pdf

**Abstract:**

Body-coupled powering (BCP) via the human body channel has demonstrated improved pathloss and body-area coverage over conventional approaches. This work focuses on dynamic optimization of the transmitter (hub-side) output power and frequency, to avoid power overdraw for prolonged transmitter (hub) lifetime. Power evaluation and feedback allow the transmitter to dynamically adapt its power and frequency, based on the node-specific channel and power condition, with only ~90nW overhead. This saves the overall TX power by 7×. Moreover, HV driver with simplified driving circuits is proposed in standard CMOS process, which allows for 20× improved power delivery (at 105cm) while saving 23% of the TX power consumption. The body-coupled power transceiver (TRX) ICs are implemented and measured in 40nm CMOS process.

Body-Coupled Power Transceiver with Node-Specific Body-Area Powering

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9018.pdf

**Abstract:**

This paper presents a fully integrated dual-band transceiver (TRX) with mutually-coupled on-chip antennas for implantable and wearable devices. It operates at 915 MHz and 2.4 GHz in both transmit and receive modes to enable bidirectional communication between medical and consumer electronics using a single chip. The TRX is fabricated in 180 nm CMOS along with a power management unit (PMU) with a size of 2.4x1.9 mm2. The transmitter (TX) consists of a mutually-coupled dual-band oscillator and uses the on-chip antennas as the inductors of the oscillators. The maximum uplink data rates of the TXs are 20 Mb/s and 40 Mb/s for 915 MHz and 2.4 GHz, respectively, with corresponding TX efficiencies of 62 pJ/b and 35 pJ/b. The maximum achievable downlink data rates are 2 Mb/s and 1 Mb/s for 915 MHz and 2.4 GHz, respectively, resulting in 2 pJ/b and 4 pJ/b of energy efficiencies. Importantly, the proposed TRX achieves uplink and downlink communication ranges of 30 cm and 17 cm for the 915 MHz band, and of 38 cm and 2 cm for the 2.4 GHz band, respectively.

Dual-Band Transceiver with Mutually-Coupled On-Chip Antennas for Implantable/Wearable Devices

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9076.pdf

**Abstract:**

This paper presents a widely tunable bandpass filter (BPF) that can autonomously adapt its gain to the power level of signals present within its passband. Similar to outphasing amplifiers, the filter realizes reconfigurable gain by splitting the input signal using two N-path filters into two components of equal and opposite phases (±Φ). The components are then subtracted at the filter output to reconstruct the original signal with a gain value proportional to sin(Φ).

A Self-Adaptive 4th-Order Filter Based on Tunable N-Path Filters

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9294.pdf

**Abstract:**

This paper presents a 27.0-30.5 GHz sub-sampling PLL implemented in a 0.18um SiGe BiCMOS process. The PLL incorporates an improved Class-C VCO with a supply-side 2nd-harmonic common-mode resonance and a completely floating, transformer-based 3rd-harmonic differential-mode resonance. Despite the generations-old CMOS devices and their amplified penalty at higher frequencies, the prototype achieves sub-50fs RMS jitter at 30GHz when integrated from 1kHz to 100MHz offsets, outperforming recent state-of-the-arts in advanced CMOS nodes with similar output frequencies. The PLL achieves an excellent jitter FoM of -247.8dB when the FLL is turned on and -250.4dB when off.

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