Italy

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9179.pdf

**Abstract:**

This paper presents a buck converter with sub-nW quiescent power, high efficiency, and a wide dynamic range for ultra-low-power (ULP) IoT SoCs. To optimize the SoC power consumption, the buck converter supports fast dynamic voltage and frequency scaling (DVFS) and enables fast load-transient response (FLTR) through asynchronous control. In addition, the buck converter is fully self-contained with all features integrated on chip including a proposed adaptive deadtime controller. Fabricated in 65nm CMOS, measurement results show the buck converter has an 802pW quiescent power at 1.5V input voltage and a 93% peak efficiency. The measured dynamic range is from 0.5nW to 2.75mW, which is over 6 orders of magnitude. The measured voltage droop is 54mV for a 45nA-to-1mA load current step thanks to the asynchronous load-transient detector. The buck converter achieves the highest efficiency and widest dynamic range among all the state-of-the-art sub-nW switching voltage regulators, which makes it well suited for power management in ULP SoCs.

ESSCIRC ESSDERC 2021

An 802pW 93% Peak Efficiency Buck Converter with 5.5×106 Dynamic Range Featuring Fast DVFS and Asynchronous Load-Transient Control

fast load-transient response

asynchronous control

fast dvfs

wide dynamic range

sub-nw quiescent power

buck converter

high efficiency

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021<br>
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021<br>
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**


To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





technical paper

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9256.pdf

**Abstract:**

This paper presents a single-chip high-voltage transceiver ASIC for low-ﬁeld NMR spectroscopy. The chip integrates an adjustable high-voltage (HV) H-bridge power ampliﬁer (PA) with a PLL frequency synthesizer and a quadrature low intermediate frequency (low-IF) receiver, achieving a measured input-referred voltage noise density of 1.1 nV/√Hz. The operating frequency of the chip is from 0.1 MHz to 200 MHz, supporting all relevant Larmor frequencies for low-ﬁeld mobile and portable NMR. The PA consists of four isolated 50 V NMOS transistors, isolated gate drivers with a digitally adjustable deadtime control, high-frequency level shifters, and a TX-control logic that supports bootstrapping of the integrated high-side drivers. The output current can be deﬁned by an adjustable voltage supply from 0 V to 50 V, delivering a maximum current of 2.0 A_pp into a non-tuned 3 mm NMR coil and up to 8.3 A_pp into a parallel tuned NMR coil. Inside a custom-designed 1.1 T portable NMR magnet, the system achieves a spin sensitivity of 1.1 × 10^16 spins/√Hz and a concentration sensitivity of 1 mM/√Hz.

A 0.1 MHz to 200 MHz High-Voltage CMOS Transceiver for Portable NMR Systems with a Maximum Output Current of 2.0 App

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9211.pdf

**Abstract:**

We present a tunneling magnetoresistive (TMR) sensing microsystem consisting of a low flicker noise TMR sensor and a custom integrated readout frontend. The proposed sensor readout circuit introduces a novel ultra-low-noise current biasing scheme for the TMR sensor, which achieves a very low current noise floor of 2.2 pA/sqrt(Hz) for a 1mA biasing current. The TMR output voltage is processed by a differential readout scheme to improve the baseline-to-signal ratio. The microsystem also features an on-chip 10-bit current DAC that allows compensating for the large process variations in the TMR base resistance value. The readout chip is manufactured in a 180nm SOI CMOS technology and heterogeneously integrated with the TMR sensor. The readout chain provides a thermal noise floor of 4 nV/sqrt(Hz), while, together with the biasing scheme, consuming a total power of 38mW. The complete sensor system consisting of the TMR and the readout circuit provides a state-of-the-art magnetic field noise floor of 120 pT/sqrt(Hz).

A Readout Circuit for Tunnel Magnetoresistive Sensors Employing an Ultra-Low-Noise Current Source

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9201.pdf

**Abstract:**

This paper introduces a new architecture of a discrete-time charge-rotating low-pass filter (LPF) which achieves a high-order of filtering and improves its stop-band rejection while maintaining a reasonable duty cycle of the main clock at 20%. Its key innovation is a linear interpolation within the charge-accumulation operation. Fabricated in 28-nm CMOS, the proposed IIR LPF demonstrates a 1--9.9 MHz bandwidth programmability and achieves a record-high 120 dB stop-band rejection at 100 MHz while consuming merely 0.92 mW. The in/out-of-band IIP3 is +18.6/+26.6 dBm.

A Charge-Rotating IIR Filter with Linear Interpolation and High Stop-Band Rejection

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9190.pdf

**Abstract:**

This paper presents the design and the validation of a continuous-time 2nd-order analog filter with 40 MHz -3 dB cut-off frequency. The circuit synthesizes a pair of conjugated complex poles by leveraging the inductive behaviour of the source node of the folded branch of a differential amplifier. This circuital technique dominates noise power and harmonic distortion by a simple input MOS transistor pair of a differential stage, resulting in 7-nV/√Hz in-band Input Referred Noise power spectral density and 69 dB output Dynamic Range. Moreover, this solution enables the introduction of gain in the filter, relaxing gain, power, and bandwidth requirements of the following stages in cascade structure. A filter prototype is realized in 28 nm CMOS, consuming 309 µW from 1.1 V and performing –6 dBm in-band Input IP3 at 20 dB passband gain.

309-µW 40-MHz 20-dB-Gain Analog Filter in 28nm-CMOS

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9089.pdf

**Abstract:**

This work introduces a class of voltage references able to operate down to 3.2 pW and 0.2-V supply for energy harvesting with relaxed or suppressed voltage regulation (direct harvesting). Inherent wafer-to-wafer process sensitivity limitations and effect of process corners in deep sub-threshold are mitigated via a selection/combination of circuit replicas driven by a process sensor, at zero testing effort and trimming. A 180-nm testchip shows 1.6% process sensitivity (including wafer-to-wafer variations), 60.7-µV/V line sensitivity, and 34.9-µV/°C temperature coefficient, leading to 1.4-mV overall accuracy across corner wafers.

A 3.2-pW, 0.2-V Trimming-Less Voltage Reference with 1.4-mV Across-Wafer Total Accuracy

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9299.pdf

**Abstract:**

In this paper, we propose an in-memory True Random Number Generator (TRNG) using Voltage-Controlled MRAM that doesn’t require calibration of the writing pulse’s width and amplitude. Previous solution using Spin Transfer Torque (STT) MRAM requires calibration for every MTJ, thus making the multi-row random number generation inside the memory impossible. We also propose a 100% relative throughput digital bias correction circuit that doesn’t degrade bit rate. The VC-MTJs are fabricated in CMOS BEOL compatible process with an 80 nm diameter and high TMR ratio of 160%. MRAM array circuits and bias correction circuits are fabricated in 65 nm CMOS technology and wire-bonded with the VC-MTJ devices. Multiple VC-MTJs are tested and shown to pass all NIST randomness tests.

A Calibration-Free In-Memory True Random Number Generator Using Voltage-Controlled MRAM

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9307.pdf

**Abstract:**

This paper investigates reconfigurable physical unclonable function (PUF) design by exploiting the polarization switching variation and stochasticity in ferroelectric field-effect-transistors (FeFETs). The proposed PUFs include 1-transistor/cell (1T/C) and 2T/C designs. The denser 1T/C PUF splits random ‘0’ and ‘1’ states using a tactically pre-defined reference. The 2T/C PUF needs no dedicated references and obtains unbiased random states by differentiating two FeFETs under a proposed sensing error cancellation scheme. Experimental measurements have shown the uniform randomness, uniqueness, repeatability and reconfigurability of the response. Further simulations using an experimentally calibrated multi-domain FeFET model show high energy efficiency and robustness on design parameters.

Exploiting FeFET Switching Stochasticity for Low-Power Reconfigurable Physical Unclonable Function

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9243.pdf

**Abstract:**

A charge-domain SRAM-based CIM macro is proposed to implement efficient neural accelerator with variable input/weight/output precisions. A versatile All-Around-Wire-Capacitor (AAWC) is introduced to enable accurate charge-domain MAV operation with 1-5 bit variable-precision weight capability with 10T SRAM cell structure. The AAWC also allows variable-precision array-embedded 1-5 bit digital-to-analog (DA) conversion for input, and 1-6 bit analog-to-digital (AD) conversion for output without additional passive devices. Such array-embedded DA/AD conversion scheme significantly reduces area overhead and simplifies peripheral circuits to achieve high array efficiency while achieving high energy efficiency of 24–330 TOPS/W.

A Charge-Domain Computation-in-Memory Macro with Versatile All-Around-Wire-Capacitor for Variable-Precision Computation and Array-Embedded DA/AD Conversions

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9200.pdf

**Abstract:**

This work presents an SRAM macro for continuous data buffering, simultaneous (always-on) in-memory computing for area- and energy-efficient event detection, and energy-efficient bulk read upon event occurrence for off-memory deeper data insights. The bitcell with non-precharged operation enables signed current summing for energy-efficient inference, 90% bitline activity reduction in conventional reads without any data prediction circuitry. Hence, the proposed SRAM uniquely enhances energy efficiency both in read access and in-memory compute operation. The proposed SRAM achieves 109TOPS/mm2 area efficiency and 749-1,459TOPS/W energy efficiency in 28nm under neural net workloads.

SRAM with In-Memory Inference and 90% Bitline Activity Reduction for Always-on Sensing with 109 TOPS/mm2 and 749-1,459 TOPS/W in 28nm

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9198.pdf

**Abstract:**

This paper presents a reconfigurable in-memory computing macro for processing neural networks using 7T SRAM bitcells with decoupled read with an extra NMOS transistor. Zero inputs and weights are skipped based on the dual bitcell structure for saving energy. Binary-searching ADCs are embedded into every columns of the bitcell array and they enhance the performance and energy-efficiency. There are three types of bitcells per each bitcell column for processing dot-products, calibrating offsets, and performing a binary-searching ADC operation column-by-column. A test-chip is fabricated using 65nm, and the linearity of 128x column-based neurons are measured.

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