Italy

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9292.pdf

**Abstract:**

This paper presents dual-layer proton irradiation profile to improve the thermal stability of high-resistivity substrate formed by low-fluence proton irradiation. Dual-layer irradiation uses targeted irradiation to the Si-SiO2 interface to reduce the fluence required for preventing the formation of conduction layer after annealing. Thermal stability of effective substrate resistivity is evaluated indirectly through inductor Q-factor measurement before and after annealing at 260°C for 1 minute. With the same total fluence, measurement result shows the proposed dual-layer irradiation profile can suppress post-anneal Q-factor degradation from 17% to 1%. The required active devices margin from irradiated area is also reduced by 26%.

ESSCIRC ESSDERC 2021

Dual-Layer Proton Irradiation for Creating Thermally-Stable High-Resistivity Region in Si CMOS Substrate

low fluence

proton irradiation

thermal stability

#### Welcome to the 62nd IEEE International Reliability Physics Symposium (IRPS)! 
**The 2024 IEEE International Reliability Physics Symposium (IRPS) was held in Dallas, Texas from April 14 to 18, 2024.** 

[![](https://assets.underline.io/uploads/markdown_image/1/image/9cc005f94b4ba4a81918eb49e0a51057.png)](https://underline.io/events/446/reception)
[![](https://assets.underline.io/uploads/markdown_image/1/image/acae953ba70ae2a57eed7b0250d6dd7d.png)](https://www.irps.org/)
[![](https://assets.underline.io/uploads/markdown_image/1/image/e1806748f2fc69f825e596872a7afdfd.png)](https://drive.google.com/drive/folders/1SmhpLZD9swYxrfP0TYF6327QTIciy3tV?usp=drive_link)
 

**[IRPS 2024 eGuide](https://drive.google.com/file/d/1DHxkWbafodK_D2HlDi7lwRK7KatgBgBD/view?usp=drive_link)** 
Please save the zip file locally and click the "start.pdf" to view the file. 
 
**IRPS 2024 General Chair Welcome Message**

On behalf of the Management Committee of the IEEE International Reliability Physics Symposium (IRPS) and the IRPS Board of Directors, it gives me great pleasure to extend a warm welcome to all who are planning to attend the IRPS 2024, scheduled to take place from April 14-18, 2024, in Dallas, TX. 
Over its 62-year history, IRPS has solidified its position as the premiere conference for engineers and scientists to present new and original work in the field of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and other parts of the world, IRPS aims to deepen our understanding of reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS offers diverse opportunities for attendees to enhance their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The IRPS 2024 technical activities will begin with two days of a total of twenty tutorial sessions covering a broad spectrum of emerging reliability topics beyond CMOS device, circuit and system reliability. These sessions are devoted to both newcomers as well as experts. Three reliability Year in Review (YIR) talks focusing on neuromorphic computing, dielectric breakdown in leading edge devices, and GaN technology will be provided on Monday after the tutorials.

The IRPS 2024 technical program will feature four distinguished keynote talks in the plenary sessions delivered by Prof. Shinichi Takagi from The University of Tokyo and Dr. Su Jin Ahn from Samsung on Tuesday, Dr. Rajeev Malik from IBM on Wednesday, and Dr. Sameer Pendharkar from Texas Instruments on Thursday. The technical program, organized into three parallel tracks, consists of contributed and seventeen invited papers from leaders in industry and academia. Additionally, two invited talks by recipients of paper awards from our sister conferences, European Symposium on Reliability of Electron Device Failure Physics and Analysis (ESREF) 2023 and the International Integrated Reliability Workshop (IIRW) 2023, will be given in the technical program. 

Tuesday evening will host ten workshops, offering an opportunity for in-depth, face-to-face discussions on emerging reliability challenges, including the three IRPS 2024 focus topics. A poster session will be held in the Austin Ranch outside the symposium building on Wednesday evening. Both events are sure to be lively. The IRPS 2024 and the International ESD Workshop (IEW) will be co-hosted with IEW registrants participating in both IRPS and IEW programs.

The IRPS 2024 will adopt a hybrid conference style, allowing virtual access to live oral presentations hosted by the Underline. Real-time streaming of all technical events (excluding Workshops and Posters) will be available in the US Central Timezone, providing virtual attendees with Q&A opportunities. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees after the symposium. All authors will be presenting in person.

Finally, I would like to extend my extreme gratitude to our patrons, exhibitors, and all participants for their invaluable support, which makes IRPS successful. 

Please enjoy the IRPS 2024!

Koji Eriguchi, General Chair 
of 2024 IRPS Management Committee
 
**About IRPS** 
The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

You need to log in with the email address you registered with. Access credentials have been sent to your email. 

Please be sure to check your spam and other email folders if you do not see an email confirmation right away.

Please log in to explore this event.

It looks like you are not registered for this event. 

To access the site please register [**here**](https://www.irps.org/registration-fees). 

Please register!

IRPS 2024 Main Conference

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. 

technical paper

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9336128

**Abstract:**

Generative Adversarial Networks (GAN) consists of multiple deep neural networks cooperating and competing each other. Due to their complex architectures, training GANs requires huge computations and external memory accesses. However, retraining GANs with user-specific data is critical on mobile devices because the pretrained model outputs distorted images under user-specific conditions. This paper proposes an FPGAbased GAN training accelerator to enable energy-efficient domain specific optimization of GAN with user’s local data. A SELRET(Selective-Layer Retraining) is proposed to reduce the computation by 69% through selecting layers that are effective in enhancing the quality of the output. Moreover, ROLIN (Reordering Layers for Instance Normalization) is proposed to reduce the external memory accesses of intermediate data. The design is implemented on Intel’s Cyclone V, showing 51 GFLOPS peak performance with 10.04GFLOPS/W energy-efficiency for face modification of 256×256 image.

An Energy-Efficient GAN Accelerator with On-Chip Training for Domain Specific Optimization

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9199903

**Abstract:**

In this paper, a broad-purpose compute-inmemory solution (±CIM) able to handle arbitrary sign in both inputs/features and weights/coefficients is introduced. The ability to operate on arbitrary sign and under variable precision on both operands enables a wide range of applications, ranging from conventional neural networks to digital signal processing and monitoring. The ±CIM pipelined architecture, the reconfigurable row encoder and the adoption of a commercial 2-port bitcell allow uninterrupted memory availability for conventional read/write, even when performing in-memory computations.

Broad-Purpose In-Memory Computing for Signal Monitoring and Machine Learning Workloads

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9491142

**Abstract:**

Time-domain computing-in-memory (TD-CIM) architectures have three challenges for accelerating multi-bit DNNs due to their inferior bit-split convolution: poor network adaptability, massive redundant computations, and high quantization energy and error. This work firstly proposes a unique-weight kernel decomposition based convolution method for accelerating multi-bit DNNs. Then a TD-CIM based processor is designed with three techniques to address above challenges: 1) Cross-flipping based kernel decomposer to reduce memory accesses, 2) Dual-mode complementary predictor to remove redundant computations, 3) Activation-weight-adaptive pulse quantizer to reduce quantization energy and error. Fabricated in 28nm and evaluated with 1-to-8bit DNN, the processor achieves 2.4-to-152.7TOPS/W peak energy efficiency.

A Time-Domain Computing-in-Memory Based Processor Using Predictable Decomposed Convolution for Arbitrary Quantized DNNs

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9203868

**Abstract:**

A 6.4 nW 1.7 % relative inaccuracy (R-IA) CMOS sub-thermal drain voltage-based temperature sensor is proposed. The proposed stabilized sub-thermal drain voltage current generator achieves a highly linear PTAT output without nonlinearity fitting or post-fabrication trimming, and increases the accuracy of the sensor. The combination of the current generator and a frequency-locked-loop relaxes the tradeoff between power and temperature stability of the current-to-frequency converter, and achieves supply-voltage-independent operation. Measured results of the prototype fabricated in a 65 nm CMOS process show that the proposed temperature sensor has a -1.0/+0.7 °C inaccuracy (= R-IA of 1.7 %) while achieving a resolution of 75 mK over a temperature range of -30 to 70 °C. The line sensitivity of the sensor is 2.8 °C/V.

A 6.4 nW 1.7% Relative Inaccuracy CMOS Temperature Sensor Utilizing Sub-Thermal Drain Voltage Stabilization and Frequency Locked Loop

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9129800

**Abstract:**

A CMOS Voltage Level Detector (VLD) circuit is proposed for IoT systems which operates near the minimum energy point. It can accurately detect VCC levels of 550-640mV, making it one of the lowest voltage VLDs reported to date. A novel pull-up circuit is utilized to accurately detect fast VCC ramps of 10’s of micro seconds, which are faster than the power-up of the VLD itself. This feature enables it to operate at a low power consumption of 2.6uW. A low voltage, charge-pumped bandgap reference is utilized with a highly accurate comparator to achieve a 35mV variation across temperature and a random variation sigma of 1.68mV. This circuit is one of the lowest voltage, most highly accurate and fastest ramp-detect VLDs that have been reported in the literature.

An Accurate 0.55V 2.6 µW Voltage Level Detector

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9141323

**Abstract:**

This letter presents a low-power dynamic comparator for ultralow power applications. The prototype is designed in a 65-nm CMOS process with a supply voltage of 1 V and is compared against the widely used double tail latch comparator in terms of power consumption and input referred rms noise. The addition of cross-coupled devices to the input differential pair prevents the comparator internal nodes from fully discharging to ground in contrast to the conventional architecture. This reduces the power consumption while achieving similar noise levels. Measurements demonstrate that the proposed comparator achieves an input referred rms noise voltage of 220 µV against 210 µV for the conventional comparator with a 30% reduction in power. The proposed circuit consumes 0.19-pJ energy per comparison.

A Low-Power 1-V Supply Dynamic Comparator

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9154469

**Abstract:**

An electrochemical sensor signal acquisition chain consisting of a multichannel bidirectional current-mirror-based potentiostat and a multiplexed current-input delta–sigma ADC is presented. To enable the integration of the circuit into wirelessly powered point-of-care (PoC) diagnostics, a low-voltage and low-power implementation of the circuit is proposed. This is achieved by the use of a class-AB-amplifier based sensor front-end, which keeps the power and voltage headroom consumption at a minimum. Output stage current replication in the front-end amplifier enables bidirectional current sensing without additional measures. The proposed circuit achieves a wide dynamic range and the highest power efficiency among similar systems.

A Bidirectional Current-Mirror-Based Potentiostat Using a Slice-Based Class-AB Amplifier

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9129816

**Abstract:**

Active rectifier, biomedical implantable devices, coarsefine, delay compensation, wireless power transfer (WPT). This letter presents an active rectiﬁer with SAR-assisted coarse-ﬁne adaptive digital delay compensation technique for biomedical implantable devices. Both on- and off-delays are compensated by adjusting the comparator offset. In order to achieve accurate zero-voltage switching against process, voltage, and temperature variations, a two-step coarse-ﬁne digital tuning method is introduced. The coarse-tuning phase and the ﬁne-tuning phase are controlled by a 7-bit SAR controller and a 3-bit bidirectional counter, respectively. The proposed technique could avoid reverse current and achieve maximum conduction time for power switches. Meanwhile, it is suitable for compensating power switch with large on/off-delay variation.

A 13.56-MHz Active Rectifier with SAR-Assisted Coarse-Fine Adaptive Digital Delay Compensation for Biomedical Implantable Devices

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9152041

**Abstract:**

A multichannel impedance-sensing CMOS chip for the readout of non-invasive light detectors in Silicon Photonics is presented. The performance of the lock-in phase-sensitive demodulator is improved thanks to a capacitive feedback transimpedance amplifier (TIA) equipped with an active discharge network, able to keep a DC output offset lower than 3 mV for leakage currents up to 4 nA while injecting a noise lower than 40 fA/sqrt(Hz). The addition of a sensor capacitance compensation system at the input of the chip allows a 30-fold increase of the stimulation amplitude, enabling the tracking of sub-picoSiemens conductance variations on a baseline of few uS, with a bandwidth of 70 Hz. The chip performance opens the way to multipoint monitoring of complex photonic systems, addressing the challenges posed by the growing complexity of these architectures.

Wide Dynamic Range Multichannel Lock-in Amplifier for Contactless Optical Sensors with Sub-Ps Resolution

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9023.pdf

**Abstract:**

This paper focuses on the comparison of various advanced substrates such as trap-rich (TR), porous silicon (PSi), gold-doped (Au-Si) and smart-implants PN-junction (DP) in terms of RF performances. Both small- and large-signal measurements were performed, including the study of the influence of temperature and bias voltage. The purpose of this paper is to provide an overview of the characteristics of these multiple substrates to facilitate design choices for RF-IC applications.

Downloads

Next from ESSCIRC ESSDERC 2021

An Energy-Efficient GAN Accelerator with On-Chip Training for Domain Specific Optimization

Similar lecture

Reliability Assessment of a-IGZO and ZnO Thin Film Transistors (TFTs) to X-ray irradiation

.css-70qvj9{display:-webkit-box;display:-webkit-flex;display:-ms-flexbox;display:flex;-webkit-align-items:center;-webkit-box-align:center;-ms-flex-align:center;align-items:center;}Downloads

Next from ESSCIRC ESSDERC 2021

An Energy-Efficient GAN Accelerator with On-Chip Training for Domain Specific Optimization

Similar lecture

Reliability Assessment of a-IGZO and ZnO Thin Film Transistors (TFTs) to X-ray irradiation

Downloads