Italy

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9072.pdf

**Abstract:**

Dark Count Rate (DCR) in Single-Photon Avalanche Diodes (SPAD) in Complementary Metal-Oxide Semiconductor technology is characterized and analyzed with a comprehensive simulation methodology. Based on a series of measurements of SPAD with various architectures, on an extended range of voltages and temperatures, the DCR measurements are correlated to the spatial localization of traps within the device and their parameters. To this aim, process and electrical simulations using Technology Computer-Aided Design (TCAD) tools are combined with an in-house McIntyre solver to compute the breakdown probability (Pt). The traps are accounted for using thermal SRH carrier generation-recombination mechanism which is coupled with the position-dependent breakdown probability. This rigorous methodology makes it possible to directly compare with DCR measurements, since only generated carriers with a non-negligible avalanche probability are considered.

ESSCIRC ESSDERC 2021

Dark Count Rate in Single-Photon Avalanche Diodes: Characterization and Modeling Study

technology computer-aided design

dark count rate

breakdown probability

single-photon avalanche diode

defects

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021<br>
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021<br>
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**


To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





technical paper

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9092.pdf

**Abstract:**

In this paper, a 4.3e- RMS low noise 4.6μm Time-of-Flight pixel based on charge domain with kTC noise removal is proposed to enhance the depth camera image quality. The pixel takes advantages of 6μm gradually doped epitaxial layer for 88.5% demodulation contrast at 200MHz and 18.5% QE at 940nm. Buried channel transfer gates are used to enable low capacitive switching and allowing best-in-class 1.4μW/pixel power consumption at 200MHz. The pixel is fully isolated due to deep trench isolation and pixel bulk is biased at several hundreds of mV for ultimate low power Time-of-Flight sensor and system. The paper describes the design of 0.54Mpix camera (672 x 804 pixels) implementing demodulation circuits robust against EMI and multi-devices interferences. The performance of an indirect Time-of-Flight system is demonstrated with 1.0% depth noise under 40kLux at 30fps.

4.6μm Low Power Indirect Time-of-Flight Pixel Achieving 88.5% Demodulation Contrast at 200MHz for 0.54MPix Depth Camera

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9214.pdf

**Abstract:**

We will present major advances in Time of Flight image sensors for consumer applications. Several innovative elements integrated into a 130nm front side illumination CMOS node reveal superior sensor performance so far only attributed to much more complex backside illumination technologies. The gate controlled pixels comprising deep trenches, buried mirrors and integrated prisms, reveal high quantum efficiency and modulation transfer function close to the physical pixel size. In-pixel common mode suppression prevents saturation even under backlight conditions. The comprehensive System on Chip integrates high speed ADCs, a flexible phase shifter, as well as current monitoring for laser safety.

Advancements in Indirect Time of Flight Image Sensors in Front Side Illuminated CMOS

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9210837

**Abstract:**

An analytical model for back bias capability including interface traps, quantum confinement, short channel effects is developed, which is in excellent agreement with TCAD simulations and measurements. The derived expressions facilitate the accurate assessment of interface trap impact on variability and also benefit the configuration of dynamics back bias for aging compensation, thereby fully leveraging the UTBB FDSOI technology.

Analytical Model for Interface Traps Dependent Back Bias Capability and Variability in Ultrathin Body and Box FDSOI MOSFETs

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9186799

**Abstract:**

In this study, a consistent analytical chargebased model for the bias-dependent variability of the drain current of organic thin-film transistors is presented. The proposed model combines both charge-carrier-numberfluctuation effects and correlated-mobility-fluctuation effects to predict the drain-current variation and is verified using experimental data acquired from a statistical population of organic transistors with various channel dimensions, fabricated on flexible polymeric substrates in the coplanar or the staggered device architecture.

Charge-Based Model for the Drain-Current Variability in Organic Thin-Film Transistors Due to Carrier-Number and Correlated-Mobility Fluctuation

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9184253

**Abstract:**

A charge-based macromodel for small-signal ac and transient analyses of organic thin-ﬁlm transistors (TFTs) is presented. Due to the comparatively small charge- carrier mobility in organic TFTs, the dynamic behavior of the gate-ﬁeld-induced carrier channel is greatly affected by the frequency of the applied gate–source and drain–source voltages. The model presented here is, therefore, based on the transmission-line model and shown to reproduce the results of frequency-dependent admittance measurements and numerical simulations of the transient switching behavior of organic TFTs fabricated in the staggered architecture with good accuracy. The model has been implemented in the hardware description language Verilog-A.

Macromodel for AC and Transient Simulations of Organic Thin-Film Transistor Circuits Including Nonquasistatic Effects

Multi-channel potentiostats are required for monitoring electrochemical processes in a time- and cost- efficient manner. State-of-the-art PCB potentiostats suffer from limited performance. Existing integrated CMOS potentiostats enable large number of parallel sensing channels, yet are still limited in the number of parallel stimulation channels and their bandwidth. The presented 40nm CMOS potentiostat chip overcomes this bottleneck with 96 individually controllable channels with 125dB current dynamic range and up to 150kHz bandwidth using an on-chip digital feedback controller. The chip supports both on-chip and off-chip electrodes allowing flexible electrode dimensions.

A 96-channel 40 nm CMOS Fully-Integrated Potentiostat for Electrochemical Monitoring

This keynote is describing the evolution of Artificial Intelligence (AI) adoption to the Edge for maximizing Data processing at the User experience level to treat as much as possible data analysis without saturating Internet traffic and Cloud data centers. Evolution of Neural Network (NN) computing through progressive usage of In Memory Computing (IMC) is also described. A few examples of Artificial Intelligence at the Edge are also commented. We then describe how at ST, we address competitive solutions for Edge AI thanks to differentiated FD-SOI CMOS technology, Phase Change Memory (PCM) embedded memory integration and advanced NN and IMC design solutions.

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